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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Diff between revs 37 and 39

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Rev 37	Rev 39
Line 61...	Line 61...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.12 2001/11/07 17:51:52 gorban`
	`// Heavily rewritten interrupt and LSR subsystems.`
	`// Many bugs hopefully squashed.`
	`//`
`// Revision 1.11 2001/10/29 17:00:46 gorban`	`// Revision 1.11 2001/10/29 17:00:46 gorban`
`// fixed parity sending and tx_fifo resets over- and underrun`	`// fixed parity sending and tx_fifo resets over- and underrun`
`//`	`//`
`// Revision 1.10 2001/10/20 09:58:40 gorban`	`// Revision 1.10 2001/10/20 09:58:40 gorban`
`// Small synopsis fixes`	`// Small synopsis fixes`
Line 229...	Line 233...
`begin`	`begin`
`counter <= #1 0;`	`counter <= #1 0;`
`state <= #1 s_send_byte;`	`state <= #1 s_send_byte;`
`end`	`end`
`else`	`else`
`counter <= #1 counter - 5'b00001;`	`counter <= #1 counter - 1'b1;`
`stx_o_tmp <= #1 1'b0;`	`stx_o_tmp <= #1 1'b0;`
`end`	`end`
`s_send_byte : begin`	`s_send_byte : begin`
`if (~\|counter)`	`if (~\|counter)`
`counter <= #1 5'b01111;`	`counter <= #1 5'b01111;`
`else`	`else`
`if (counter == 5'b00001)`	`if (counter == 5'b00001)`
`begin`	`begin`
`if (bit_counter > 3'b0)`	`if (bit_counter > 3'b0)`
`begin`	`begin`
`bit_counter <= #1 bit_counter - 1;`	`bit_counter <= #1 bit_counter - 1'b1;`
`{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};`	`{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};`
`state <= #1 s_send_byte;`	`state <= #1 s_send_byte;`
`end`	`end`
`else // end of byte`	`else // end of byte`
if (~lcr[`UART_LC_PE])	if (~lcr[`UART_LC_PE])
Line 262...	Line 266...
`state <= #1 s_send_parity;`	`state <= #1 s_send_parity;`
`end`	`end`
`counter <= #1 0;`	`counter <= #1 0;`
`end`	`end`
`else`	`else`
`counter <= #1 counter - 5'b00001;`	`counter <= #1 counter - 1'b1;`
`stx_o_tmp <= #1 bit_out; // set output pin`	`stx_o_tmp <= #1 bit_out; // set output pin`
`end`	`end`
`s_send_parity : begin`	`s_send_parity : begin`
`if (~\|counter)`	`if (~\|counter)`
`counter <= #1 5'b01111;`	`counter <= #1 5'b01111;`
Line 275...	Line 279...
`begin`	`begin`
`counter <= #1 4'b0;`	`counter <= #1 4'b0;`
`state <= #1 s_send_stop;`	`state <= #1 s_send_stop;`
`end`	`end`
`else`	`else`
`counter <= #1 counter - 5'b00001;`	`counter <= #1 counter - 1'b1;`
`stx_o_tmp <= #1 bit_out;`	`stx_o_tmp <= #1 bit_out;`
`end`	`end`
`s_send_stop : begin`	`s_send_stop : begin`
`if (~\|counter)`	`if (~\|counter)`
`begin`	`begin`
Line 294...	Line 298...
`begin`	`begin`
`counter <= #1 0;`	`counter <= #1 0;`
`state <= #1 s_idle;`	`state <= #1 s_idle;`
`end`	`end`
`else`	`else`
`counter <= #1 counter - 5'b00001;`	`counter <= #1 counter - 1'b1;`
`stx_o_tmp <= #1 1'b1;`	`stx_o_tmp <= #1 1'b1;`
`end`	`end`

`default : // should never get here`	`default : // should never get here`
`state <= #1 s_idle;`	`state <= #1 s_idle;`

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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Diff between revs 37 and 39