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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Diff between revs 61 and 70
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2001/12/17 14:46:48 mohor
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// overrun signal was moved to separate block because many sequential lsr
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// reads were preventing data from being written to rx fifo.
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// underrun signal was not used and was removed from the project.
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//
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// Revision 1.14 2001/12/03 21:44:29 gorban
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// Revision 1.14 2001/12/03 21:44:29 gorban
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// Updated specification documentation.
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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Line 322... |
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default : // should never get here
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default : // should never get here
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tstate <= #1 s_idle;
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tstate <= #1 s_idle;
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endcase
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endcase
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end // end if enable
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end // end if enable
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else
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tf_pop <= #1 1'b0; // tf_pop must be 1 cycle width
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end // transmitter logic
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end // transmitter logic
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assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
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assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
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endmodule
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endmodule
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