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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2001/10/20 09:58:40 gorban
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// Small synopsis fixes
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//
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// Revision 1.8 2001/08/24 21:01:12 mohor
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// Revision 1.8 2001/08/24 21:01:12 mohor
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// Things connected to parity changed.
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// Things connected to parity changed.
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// Clock devider changed.
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// Clock devider changed.
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//
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//
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// Revision 1.7 2001/08/23 16:05:05 mohor
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// Revision 1.7 2001/08/23 16:05:05 mohor
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module uart_wb (clk,
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module uart_wb (clk, wb_rst_i,
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wb_rst_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
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we_o, re_o // Write and read enable output for the core
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we_o, re_o // Write and read enable output for the core
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);
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);
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input clk;
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input clk;
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// WISHBONE interface
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// WISHBONE interface
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input wb_rst_i;
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input wb_rst_i;
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input wb_we_i;
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input wb_we_i;
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input wb_stb_i;
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input wb_stb_i;
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input wb_cyc_i;
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input wb_cyc_i;
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input [3:0] wb_sel_i;
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`ifdef DATA_BUS_WIDTH_8
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input [7:0] wb_dat_i; //input WISHBONE bus
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output [7:0] wb_dat_o;
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reg [7:0] wb_dat_o;
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wire [7:0] wb_dat_i;
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`else // for 32 data bus mode
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input [31:0] wb_dat_i; //input WISHBONE bus
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output [31:0] wb_dat_o;
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reg [31:0] wb_dat_o;
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wire [31:0] wb_dat_i;
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`endif
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input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
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output [7:0] wb_dat8_i;
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input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
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output wb_ack_o;
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output wb_ack_o;
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output we_o;
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output we_o;
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output re_o;
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output re_o;
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wire we_o;
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wire we_o;
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reg wb_ack_o;
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reg wb_ack_o;
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reg [7:0] wb_dat8_i;
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wire [7:0] wb_dat8_o;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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begin
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wb_ack_o <= #1 1'b0;
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wb_ack_o <= #1 1'b0;
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end
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else
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else
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begin
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// wb_ack_o <= #1 wb_stb_i & wb_cyc_i; // 1 clock wait state on all transfers
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wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers
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wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers
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end
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end
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assign we_o = wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers
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assign we_o = wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers
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assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers
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assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers
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`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
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always @(posedge clk or posedge wb_rst_i)
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if (wb_rst_i)
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wb_dat_o <= #1 0;
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else
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wb_dat_o <= #1 wb_dat8_o;
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always @(wb_dat_i)
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wb_dat8_i = wb_dat_i;
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`else // 32-bit bus
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// put output to the correct byte in 32 bits using select line
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always @(posedge clk or posedge wb_rst_i)
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if (wb_rst_i)
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wb_dat_o <= #1 0;
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else if (re_o)
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case (wb_sel_i)
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4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};
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4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};
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4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};
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4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};
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4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output
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default: wb_dat_o <= #1 0;
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// later add here selects for 16 and 32 bits
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endcase // case(wb_sel_i)
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// handle input (this will add a little timing overhead on input but it should asynchronous
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// or another one clock delay will be introduced)
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always @(wb_sel_i or wb_dat_i)
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case (wb_sel_i)
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4'b0001 : wb_dat8_i = wb_dat_i[7:0];
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4'b0010 : wb_dat8_i = wb_dat_i[15:8];
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4'b0100 : wb_dat8_i = wb_dat_i[23:16];
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4'b1000 : wb_dat8_i = wb_dat_i[31:24];
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default : wb_dat8_i = wb_dat_i[7:0];
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endcase // case(wb_sel_i)
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`endif // !`ifdef DATA_BUS_WIDTH_8
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endmodule
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endmodule
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