Line 62... |
Line 62... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.10 2001/12/03 21:44:29 gorban
|
|
// Updated specification documentation.
|
|
// Added full 32-bit data bus interface, now as default.
|
|
// Address is 5-bit wide in 32-bit data bus mode.
|
|
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
|
|
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
|
|
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
|
|
// My small test bench is modified to work with 32-bit mode.
|
|
//
|
// Revision 1.9 2001/10/20 09:58:40 gorban
|
// Revision 1.9 2001/10/20 09:58:40 gorban
|
// Small synopsis fixes
|
// Small synopsis fixes
|
//
|
//
|
// Revision 1.8 2001/08/24 21:01:12 mohor
|
// Revision 1.8 2001/08/24 21:01:12 mohor
|
// Things connected to parity changed.
|
// Things connected to parity changed.
|
Line 100... |
Line 109... |
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
|
`include "uart_defines.v"
|
|
|
module uart_wb (clk, wb_rst_i,
|
module uart_wb (clk, wb_rst_i,
|
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
|
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
|
wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
|
wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
|
we_o, re_o // Write and read enable output for the core
|
we_o, re_o // Write and read enable output for the core
|
);
|
);
|
|
|
input clk;
|
input clk;
|
|
|
Line 115... |
Line 125... |
input wb_rst_i;
|
input wb_rst_i;
|
input wb_we_i;
|
input wb_we_i;
|
input wb_stb_i;
|
input wb_stb_i;
|
input wb_cyc_i;
|
input wb_cyc_i;
|
input [3:0] wb_sel_i;
|
input [3:0] wb_sel_i;
|
|
input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line
|
|
|
`ifdef DATA_BUS_WIDTH_8
|
`ifdef DATA_BUS_WIDTH_8
|
input [7:0] wb_dat_i; //input WISHBONE bus
|
input [7:0] wb_dat_i; //input WISHBONE bus
|
output [7:0] wb_dat_o;
|
output [7:0] wb_dat_o;
|
reg [7:0] wb_dat_o;
|
reg [7:0] wb_dat_o;
|
wire [7:0] wb_dat_i;
|
wire [7:0] wb_dat_i;
|
|
reg [7:0] wb_dat_is;
|
`else // for 32 data bus mode
|
`else // for 32 data bus mode
|
input [31:0] wb_dat_i; //input WISHBONE bus
|
input [31:0] wb_dat_i; //input WISHBONE bus
|
output [31:0] wb_dat_o;
|
output [31:0] wb_dat_o;
|
reg [31:0] wb_dat_o;
|
reg [31:0] wb_dat_o;
|
wire [31:0] wb_dat_i;
|
wire [31:0] wb_dat_i;
|
`endif
|
reg [31:0] wb_dat_is;
|
|
`endif // !`ifdef DATA_BUS_WIDTH_8
|
|
|
|
output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
|
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
|
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
|
output [7:0] wb_dat8_i;
|
output [7:0] wb_dat8_i;
|
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
|
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
|
output wb_ack_o;
|
output wb_ack_o;
|
output we_o;
|
output we_o;
|
Line 137... |
Line 153... |
|
|
wire we_o;
|
wire we_o;
|
reg wb_ack_o;
|
reg wb_ack_o;
|
reg [7:0] wb_dat8_i;
|
reg [7:0] wb_dat8_i;
|
wire [7:0] wb_dat8_o;
|
wire [7:0] wb_dat8_o;
|
|
wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
|
|
reg [`UART_ADDR_WIDTH-1:0] wb_adr_is;
|
|
reg wb_we_is;
|
|
reg wb_cyc_is;
|
|
reg wb_stb_is;
|
|
reg [3:0] wb_sel_is;
|
|
wire [3:0] wb_sel_i;
|
|
reg wb_ack; // wb_ack is sampled to make 2 clock wait state between transfers
|
|
reg wre ;// timing control signal for write or read enable
|
|
|
|
// wb_ack_o FSM
|
|
reg [1:0] wbstate;
|
always @(posedge clk or posedge wb_rst_i)
|
always @(posedge clk or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i) begin
|
wb_ack_o <= #1 1'b0;
|
wb_ack_o <= #1 1'b0;
|
else
|
wbstate <= #1 0;
|
wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers
|
end else
|
|
case (wbstate)
|
|
0: begin
|
|
if (wb_stb_is & wb_cyc_is) begin
|
|
wre <= #1 0;
|
|
wbstate <= #1 1;
|
|
wb_ack_o <= #1 1;
|
|
end else begin
|
|
wre <= #1 1;
|
|
wb_ack_o <= #1 0;
|
|
end
|
|
end
|
|
1: begin
|
|
wb_ack_o <= #1 0;
|
|
wbstate <= #1 2;
|
|
wre <= #1 0;
|
|
end
|
|
2,3: begin
|
|
wb_ack_o <= #1 0;
|
|
wbstate <= #1 0;
|
|
wre <= #1 0;
|
|
end
|
|
endcase
|
|
|
|
assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
|
|
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
|
|
|
|
// Sample input signals
|
|
always @(posedge clk or posedge wb_rst_i)
|
|
if (wb_rst_i) begin
|
|
wb_adr_is <= #1 0;
|
|
wb_we_is <= #1 0;
|
|
wb_cyc_is <= #1 0;
|
|
wb_stb_is <= #1 0;
|
|
wb_dat_is <= #1 0;
|
|
wb_sel_is <= #1 0;
|
|
end else begin
|
|
wb_adr_is <= #1 wb_adr_i;
|
|
wb_we_is <= #1 wb_we_i;
|
|
wb_cyc_is <= #1 wb_cyc_i;
|
|
wb_stb_is <= #1 wb_stb_i;
|
|
wb_dat_is <= #1 wb_dat_i;
|
|
wb_sel_is <= #1 wb_sel_i;
|
|
end
|
|
|
assign we_o = wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers
|
assign wb_adr_int = wb_adr_is;
|
assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers
|
|
|
|
`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
|
`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
|
always @(posedge clk or posedge wb_rst_i)
|
always @(posedge clk or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_dat_o <= #1 0;
|
wb_dat_o <= #1 0;
|
else
|
else
|
wb_dat_o <= #1 wb_dat8_o;
|
wb_dat_o <= #1 wb_dat8_o;
|
|
|
always @(wb_dat_i)
|
always @(wb_dat_is)
|
wb_dat8_i = wb_dat_i;
|
wb_dat8_i = wb_dat_is;
|
|
|
`else // 32-bit bus
|
`else // 32-bit bus
|
// put output to the correct byte in 32 bits using select line
|
// put output to the correct byte in 32 bits using select line
|
always @(posedge clk or posedge wb_rst_i)
|
always @(posedge clk or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_dat_o <= #1 0;
|
wb_dat_o <= #1 0;
|
else if (re_o)
|
else if (re_o)
|
case (wb_sel_i)
|
case (wb_sel_is)
|
4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};
|
4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};
|
4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};
|
4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};
|
4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};
|
4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};
|
4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};
|
4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};
|
4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output
|
4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output
|
default: wb_dat_o <= #1 0;
|
default: wb_dat_o <= #1 0;
|
// later add here selects for 16 and 32 bits
|
|
endcase // case(wb_sel_i)
|
endcase // case(wb_sel_i)
|
|
|
// handle input (this will add a little timing overhead on input but it should asynchronous
|
always @(wb_sel_is or wb_dat_is)
|
// or another one clock delay will be introduced)
|
case (wb_sel_is)
|
always @(wb_sel_i or wb_dat_i)
|
4'b0001 : wb_dat8_i = wb_dat_is[7:0];
|
case (wb_sel_i)
|
4'b0010 : wb_dat8_i = wb_dat_is[15:8];
|
4'b0001 : wb_dat8_i = wb_dat_i[7:0];
|
4'b0100 : wb_dat8_i = wb_dat_is[23:16];
|
4'b0010 : wb_dat8_i = wb_dat_i[15:8];
|
4'b1000 : wb_dat8_i = wb_dat_is[31:24];
|
4'b0100 : wb_dat8_i = wb_dat_i[23:16];
|
default : wb_dat8_i = wb_dat_is[7:0];
|
4'b1000 : wb_dat8_i = wb_dat_i[31:24];
|
|
default : wb_dat8_i = wb_dat_i[7:0];
|
|
endcase // case(wb_sel_i)
|
endcase // case(wb_sel_i)
|
|
|
`endif // !`ifdef DATA_BUS_WIDTH_8
|
`endif // !`ifdef DATA_BUS_WIDTH_8
|
|
|
endmodule
|
endmodule
|