URL
https://opencores.org/ocsvn/uart16550/uart16550/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 50 |
Rev 64 |
| Line 62... |
Line 62... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.11 2001/12/06 14:51:04 gorban
|
|
// Bug in LSR[0] is fixed.
|
|
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
|
|
//
|
// Revision 1.10 2001/12/03 21:44:29 gorban
|
// Revision 1.10 2001/12/03 21:44:29 gorban
|
// Updated specification documentation.
|
// Updated specification documentation.
|
// Added full 32-bit data bus interface, now as default.
|
// Added full 32-bit data bus interface, now as default.
|
// Address is 5-bit wide in 32-bit data bus mode.
|
// Address is 5-bit wide in 32-bit data bus mode.
|
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
|
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
|
| Line 160... |
Line 164... |
reg wb_we_is;
|
reg wb_we_is;
|
reg wb_cyc_is;
|
reg wb_cyc_is;
|
reg wb_stb_is;
|
reg wb_stb_is;
|
reg [3:0] wb_sel_is;
|
reg [3:0] wb_sel_is;
|
wire [3:0] wb_sel_i;
|
wire [3:0] wb_sel_i;
|
reg wb_ack; // wb_ack is sampled to make 2 clock wait state between transfers
|
|
reg wre ;// timing control signal for write or read enable
|
reg wre ;// timing control signal for write or read enable
|
|
|
// wb_ack_o FSM
|
// wb_ack_o FSM
|
reg [1:0] wbstate;
|
reg [1:0] wbstate;
|
always @(posedge clk or posedge wb_rst_i)
|
always @(posedge clk or posedge wb_rst_i)
|
if (wb_rst_i) begin
|
if (wb_rst_i) begin
|
wb_ack_o <= #1 1'b0;
|
wb_ack_o <= #1 1'b0;
|
wbstate <= #1 0;
|
wbstate <= #1 0;
|
|
wre <= #1 1'b1;
|
end else
|
end else
|
case (wbstate)
|
case (wbstate)
|
0: begin
|
0: begin
|
if (wb_stb_is & wb_cyc_is) begin
|
if (wb_stb_is & wb_cyc_is) begin
|
wre <= #1 0;
|
wre <= #1 0;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.