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==========================================
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==========================================
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UART16750 1.0 (C) 2008-2009 Sebastian Witt
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UART16750 (C) 2008-2009 Sebastian Witt
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==========================================
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Description:
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Description:
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Implements a synthesizable 16550/16750 UART core.
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Implements a synthesizable 16550/16750 UART core.
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- None/Even/Odd parity bit generation and detection
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- None/Even/Odd parity bit generation and detection
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- Supports 1/1.5/2 stop bit generation
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- Supports 1/1.5/2 stop bit generation
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- 16/64 byte FIFO mode
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- 16/64 byte FIFO mode
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- Receiver FIFO trigger levels 1/4/8/14/16/32/56
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- Receiver FIFO trigger levels 1/4/8/14/16/32/56
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- Control lines RTS/CTS/DTR/DSR/DCD/RI/OUT1/OUT2
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- Control lines RTS/CTS/DTR/DSR/DCD/RI/OUT1/OUT2
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- Automatic flow control with RTS/CTS
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- All interrupts sources/modes
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- All interrupts sources/modes
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Todo:
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Todo:
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- Automatic flow control
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- Variable character time-out counter
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- Variable character time-out counter
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- DMA control
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Tests:
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Tests:
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A script is used to create a extensive functional stimuli file which
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A script is used to create a extensive functional stimuli file which
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can be used for simulation or real-hardware testing.
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can be used for simulation or real-hardware testing.
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Rules for FIFO generation with vendor tools:
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Rules for FIFO generation with vendor tools:
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The top-word is always available at the output (no read-request/delay).
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The top-word is always available at the output (no read-request/delay).
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Resource usage:
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* Altera Cyclone II
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o 440 LE
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o 1216 memory bits
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o Frequency: 130 MHz
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* Xilinx Spartan 3E
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o 378 Slices
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o 1 RAMB
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o Frequency: 100 MHz
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Simulation:
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It's possible to simulate and test the design with GHDL [1].
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A Makefile is available for starting the simulation. The testbench
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creates a log file (uart_log.txt).
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[1] http://ghdl.free.fr
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