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[/] [uart16750/] [trunk/] [rtl/] [vhdl/] [slib_clock_div.vhd] - Diff between revs 2 and 10
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--
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--
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-- Clock divider (clock enable generator)
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-- Clock divider (clock enable generator)
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--
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--
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-- Author: Sebastian Witt
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-- Author: Sebastian Witt
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-- Date: 27.01.2008
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-- Date: 27.01.2008
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-- Version: 1.0
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-- Version: 1.1
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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-- Boston, MA 02111-1307 USA
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-- Boston, MA 02111-1307 USA
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--
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--
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_unsigned.all;
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USE IEEE.numeric_std.all;
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USE IEEE.numeric_std.all;
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entity slib_clock_div is
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entity slib_clock_div is
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generic (
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generic (
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