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-- Boston, MA 02111-1307 USA
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-- Boston, MA 02111-1307 USA
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--
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--
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_unsigned.all;
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USE IEEE.numeric_std.all;
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USE IEEE.numeric_std.all;
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entity slib_fifo is
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entity slib_fifo is
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generic (
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generic (
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architecture rtl of slib_fifo is
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architecture rtl of slib_fifo is
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-- Signals
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-- Signals
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signal iEMPTY : std_logic; -- Internal EMPTY
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signal iEMPTY : std_logic; -- Internal EMPTY
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signal iFULL : std_logic; -- Internal FULL
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signal iFULL : std_logic; -- Internal FULL
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signal iWRAddr : std_logic_vector(SIZE_E downto 0); -- FIFO write address
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signal iWRAddr : unsigned(SIZE_E downto 0); -- FIFO write address
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signal iRDAddr : std_logic_vector(SIZE_E downto 0); -- FIFO read address
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signal iRDAddr : unsigned(SIZE_E downto 0); -- FIFO read address
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signal iUSAGE : std_logic_vector(SIZE_E-1 downto 0); -- FIFO usage
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signal iUSAGE : unsigned(SIZE_E-1 downto 0); -- FIFO usage
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-- FIFO memory
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-- FIFO memory
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type FIFO_Mem_Type is array (2**SIZE_E-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
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type FIFO_Mem_Type is array (2**SIZE_E-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
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signal iFIFOMem : FIFO_Mem_Type := (others => (others => '0'));
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signal iFIFOMem : FIFO_Mem_Type := (others => (others => '0'));
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begin
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begin
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iWRAddr <= (others => '0');
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iWRAddr <= (others => '0');
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iRDAddr <= (others => '0');
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iRDAddr <= (others => '0');
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iEMPTY <= '1';
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iEMPTY <= '1';
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elsif (CLK'event and CLK='1') then
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elsif (CLK'event and CLK='1') then
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if (WRITE = '1' and iFULL = '0') then -- Write to FIFO
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if (WRITE = '1' and iFULL = '0') then -- Write to FIFO
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iWRAddr <= iWRAddr + '1';
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iWRAddr <= iWRAddr + 1;
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end if;
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end if;
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if (READ = '1' and iEMPTY = '0') then -- Read from FIFO
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if (READ = '1' and iEMPTY = '0') then -- Read from FIFO
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iRDAddr <= iRDAddr + '1';
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iRDAddr <= iRDAddr + 1;
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end if;
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end if;
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if (CLEAR = '1') then -- Reset FIFO
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if (CLEAR = '1') then -- Reset FIFO
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iWRAddr <= (others => '0');
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iWRAddr <= (others => '0');
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iRDAddr <= (others => '0');
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iRDAddr <= (others => '0');
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begin
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begin
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if (RST = '1') then
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if (RST = '1') then
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--iFIFOMem(2**SIZE_E-1 downto 0) <= (others => (others => '0'));
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--iFIFOMem(2**SIZE_E-1 downto 0) <= (others => (others => '0'));
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elsif (CLK'event and CLK = '1') then
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elsif (CLK'event and CLK = '1') then
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if (WRITE = '1' and iFULL = '0') then
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if (WRITE = '1' and iFULL = '0') then
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iFIFOMem(CONV_INTEGER(iWRAddr(SIZE_E-1 downto 0))) <= D;
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iFIFOMem(to_integer(iWRAddr(SIZE_E-1 downto 0))) <= D;
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end if;
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end if;
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Q <= iFIFOMem(CONV_INTEGER(iRDAddr(SIZE_E-1 downto 0)));
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Q <= iFIFOMem(to_integer(iRDAddr(SIZE_E-1 downto 0)));
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end if;
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end if;
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end process;
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end process;
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-- Usage counter
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-- Usage counter
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FF_USAGE: process (RST, CLK)
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FF_USAGE: process (RST, CLK)
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elsif (CLK'event and CLK = '1') then
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elsif (CLK'event and CLK = '1') then
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if (CLEAR = '1') then
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if (CLEAR = '1') then
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iUSAGE <= (others => '0');
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iUSAGE <= (others => '0');
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else
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else
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if (READ = '0' and WRITE = '1' and iFULL = '0') then
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if (READ = '0' and WRITE = '1' and iFULL = '0') then
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iUSAGE <= iUSAGE + '1';
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iUSAGE <= iUSAGE + 1;
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end if;
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end if;
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if (WRITE = '0' and READ = '1' and iEMPTY = '0') then
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if (WRITE = '0' and READ = '1' and iEMPTY = '0') then
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iUSAGE <= iUSAGE - '1';
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iUSAGE <= iUSAGE - 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Output signals
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-- Output signals
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EMPTY <= iEMPTY;
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EMPTY <= iEMPTY;
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FULL <= iFULL;
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FULL <= iFULL;
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USAGE <= iUSAGE;
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USAGE <= std_logic_vector(iUSAGE);
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end rtl;
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end rtl;
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No newline at end of file
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No newline at end of file
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