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[/] [uart16750/] [trunk/] [rtl/] [vhdl/] [slib_mv_filter.vhd] - Diff between revs 2 and 10

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--
--
-- Majority voting filter
-- Majority voting filter
--
--
-- Author:   Sebastian Witt
-- Author:   Sebastian Witt
-- Date:     27.01.2008
-- Date:     27.01.2008
-- Version:  1.0
-- Version:  1.1
--
--
-- This code is free software; you can redistribute it and/or
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- version 2.1 of the License, or (at your option) any later version.
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-- Boston, MA  02111-1307  USA
-- Boston, MA  02111-1307  USA
--
--
 
 
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
 
USE IEEE.numeric_std.all;
USE IEEE.numeric_std.all;
 
 
 
 
entity slib_mv_filter is
entity slib_mv_filter is
    generic (
    generic (
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end slib_mv_filter;
end slib_mv_filter;
 
 
architecture rtl of slib_mv_filter is
architecture rtl of slib_mv_filter is
 
 
    -- Signals
    -- Signals
    signal iCounter     : std_logic_vector(WIDTH downto 0);     -- Sample counter
    signal iCounter     : unsigned(WIDTH downto 0);             -- Sample counter
    signal iQ           : std_logic;                            -- Internal Q
    signal iQ           : std_logic;                            -- Internal Q
 
 
begin
begin
    -- Main process
    -- Main process
    MV_PROC: process (RST, CLK)
    MV_PROC: process (RST, CLK)
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        elsif (CLK'event and CLK='1') then
        elsif (CLK'event and CLK='1') then
            if (iCounter >= THRESHOLD) then                     -- Compare with threshold
            if (iCounter >= THRESHOLD) then                     -- Compare with threshold
                iQ <= '1';
                iQ <= '1';
            else
            else
                if (SAMPLE = '1' and D = '1') then              -- Take sample
                if (SAMPLE = '1' and D = '1') then              -- Take sample
                    iCounter <= iCounter + '1';
                    iCounter <= iCounter + 1;
                end if;
                end if;
            end if;
            end if;
 
 
            if (CLEAR = '1') then                               -- Reset logic
            if (CLEAR = '1') then                               -- Reset logic
                iCounter  <= (others => '0');
                iCounter  <= (others => '0');

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