| Line 1... |
Line 1... |
--
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--
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-- UART 16750
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-- UART 16750
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--
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--
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-- Author: Sebastian Witt
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-- Author: Sebastian Witt
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-- Date: 29.01.2008
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-- Date: 29.01.2008
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-- Version: 1.3
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-- Version: 1.4
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--
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--
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-- History: 1.0 - Initial version
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-- History: 1.0 - Initial version
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-- 1.1 - THR empty interrupt register connected to RST
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-- 1.1 - THR empty interrupt register connected to RST
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-- 1.2 - Registered outputs
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-- 1.2 - Registered outputs
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-- 1.3 - Automatic flow control
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-- 1.3 - Automatic flow control
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-- 1.4 - De-assert IIR FIFO64 when FIFO is disabled
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--
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--
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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| Line 401... |
Line 402... |
UART_IS_DSR: slib_input_sync port map (CLK, RST, DSRN, iDSRNs);
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UART_IS_DSR: slib_input_sync port map (CLK, RST, DSRN, iDSRNs);
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UART_IS_DCD: slib_input_sync port map (CLK, RST, DCDN, iDCDNs);
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UART_IS_DCD: slib_input_sync port map (CLK, RST, DCDN, iDCDNs);
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UART_IS_RI: slib_input_sync port map (CLK, RST, RIN, iRINs);
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UART_IS_RI: slib_input_sync port map (CLK, RST, RIN, iRINs);
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-- Input filter for UART control signals
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-- Input filter for UART control signals
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UART_IF_CTS: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn);
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UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn);
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UART_IF_DSR: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn);
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UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn);
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UART_IF_DCD: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn);
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UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn);
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UART_IF_RI: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iRINs, iRIn);
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UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iRINs, iRIn);
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-- Sync. input synchronization
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-- Sync. input synchronization
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UART_SIS: process (CLK, RST)
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UART_SIS: process (CLK, RST)
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begin
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begin
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if (RST = '1') then
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if (RST = '1') then
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| Line 489... |
Line 490... |
iIIR_ID0 <= iIIR(1);
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iIIR_ID0 <= iIIR(1);
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iIIR_ID1 <= iIIR(2);
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iIIR_ID1 <= iIIR(2);
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iIIR_ID2 <= iIIR(3);
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iIIR_ID2 <= iIIR(3);
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iIIR_FIFO64 <= iIIR(5);
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iIIR_FIFO64 <= iIIR(5);
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iIIR(4) <= '0';
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iIIR(4) <= '0';
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iIIR(5) <= iFCR_FIFO64E;
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iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0';
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iIIR(6) <= iFCR_FIFOEnable;
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iIIR(6) <= iFCR_FIFOEnable;
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iIIR(7) <= iFCR_FIFOEnable;
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iIIR(7) <= iFCR_FIFOEnable;
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-- Character timeout indication
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-- Character timeout indication
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UART_CTI: process (CLK, RST)
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UART_CTI: process (CLK, RST)
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| Line 717... |
Line 718... |
iMSR_dDSR <= '1';
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iMSR_dDSR <= '1';
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elsif (iMSRRead = '1') then
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elsif (iMSRRead = '1') then
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iMSR_dDSR <= '0';
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iMSR_dDSR <= '0';
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end if;
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end if;
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-- Trailing edge RI
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-- Trailing edge RI
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if (iRInRE = '1') then
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if (iRInFE = '1') then
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iMSR_TERI <= '1';
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iMSR_TERI <= '1';
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elsif (iMSRRead = '1') then
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elsif (iMSRRead = '1') then
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iMSR_TERI <= '0';
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iMSR_TERI <= '0';
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end if;
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end if;
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-- Delta DCD
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-- Delta DCD
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