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--
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--
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-- UART 16750
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-- UART 16750
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--
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--
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-- Author: Sebastian Witt
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-- Author: Sebastian Witt
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-- Date: 29.01.2008
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-- Date: 29.01.2008
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-- Version: 1.0
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-- Version: 1.1
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--
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--
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-- History: 1.0 - Initial version
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-- History: 1.0 - Initial version
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-- 1.1 - THR empty interrupt register connected to RST
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--
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--
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- THR empty interrupt
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-- THR empty interrupt
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UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => RST, D => iLSR_THRE, RE => iLSR_THRERE);
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UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => RST, D => iLSR_THRE, RE => iLSR_THRERE);
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UART_IIC_THREI: process (CLK, RST)
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UART_IIC_THREI: process (CLK, RST)
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begin
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begin
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if (RST = '1') then
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if (RST = '1') then
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iTHRInterrupt <= '0';
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elsif (CLK'event and CLK = '1') then
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elsif (CLK'event and CLK = '1') then
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if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and iDIN(1) = '1' and iLSR_THRE = '1')) then
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if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and iDIN(1) = '1' and iLSR_THRE = '1')) then
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iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable
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iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable
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elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then
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elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then
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iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write
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iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write
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