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[/] [uart16750/] [trunk/] [sim/] [rtl_sim/] [bin/] [uart_test_stim.pl] - Diff between revs 12 and 14

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`# Create stimulus/test file for 16550/16750 compatible UART cores`	`# Create stimulus/test file for 16550/16750 compatible UART cores`
`#`	`#`
`# Author: Sebastian Witt`	`# Author: Sebastian Witt`
`# Date: 06.02.2008`	`# Date: 06.02.2008`
`# Version: 1.3`	`# Version: 1.4`
`# License: GPL`	`# License: GPL`
`#`	`#`
`# History: 1.0 - Initial version`	`# History: 1.0 - Initial version`
`# 1.1 - Update`	`# 1.1 - Update`
`# 1.2 - FIFO test update`	`# 1.2 - FIFO test update`
`# 1.3 - Automatic flow control tests`	`# 1.3 - Automatic flow control tests`
	`# 1.4 - FIFO 64 tests`
`#`	`#`


`#`	`#`
`# Global control settings`	`# Global control settings`
`#`	`#`
`use constant CYCLE => 30e-9; # Cycle time`	`use constant CYCLE => 30e-9; # Cycle time`
`#use constant CYCLE => 1e-9; # Cycle time`	`#use constant CYCLE => 1e-9; # Cycle time`
`use constant LOCAL_LOOP => 1; # Use UART local loopback`	`use constant LOCAL_LOOP => 1; # Use UART local loopback`
`use constant INITREGS => 1; # Initialize registers`	`use constant INITREGS => 1; # Initialize registers`
`#use constant INITREGS => 0; # Initialize registers`	`use constant TEST_CONTROL => 1; # Test control lines`
	`use constant TEST_INTERRUPT => 1; # Test interrupts`
	`use constant TEST_DEFAULT => 1; # Test standard modes`
	`use constant TEST_FIFO => 1; # Test 64 byte FIFO mode`
	`use constant TEST_FIFO64 => 1; # Test 64 byte FIFO mode`
`use constant TEST_AFC => 1; # Test automatic flow control`	`use constant TEST_AFC => 1; # Test automatic flow control`
`use constant UART_ADDRESS => 0x3f8; # UART base address`	`use constant UART_ADDRESS => 0x3f8; # UART base address`

`# Prototypes`	`# Prototypes`
`sub logmessage($); # Message`	`sub logmessage($); # Message`
Line 68...	Line 73...
`IIR_FE => 0xC0,`	`IIR_FE => 0xC0,`
`FCR_FE => 0x01,`	`FCR_FE => 0x01,`
`FCR_RXFR => 0x02,`	`FCR_RXFR => 0x02,`
`FCR_TXFR => 0x04,`	`FCR_TXFR => 0x04,`
`FCR_DMS => 0x08,`	`FCR_DMS => 0x08,`
`FCR_F64E => 0x10,`	`FCR_F64E => 0x20,`
`FCR_RT1 => 0x00,`	`FCR_RT1 => 0x00,`
`FCR_RT4 => 0x40,`	`FCR_RT4 => 0x40,`
`FCR_RT8 => 0x80,`	`FCR_RT8 => 0x80,`
`FCR_RT14 => 0xC0,`	`FCR_RT14 => 0xC0,`
	`FCR_RT16 => 0x40,`
	`FCR_RT32 => 0x80,`
	`FCR_RT56 => 0xC0,`
`LCR_WLS5 => 0x00,`	`LCR_WLS5 => 0x00,`
`LCR_WLS6 => 0x01,`	`LCR_WLS6 => 0x01,`
`LCR_WLS7 => 0x02,`	`LCR_WLS7 => 0x02,`
`LCR_WLS8 => 0x03,`	`LCR_WLS8 => 0x03,`
`LCR_STB => 0x04,`	`LCR_STB => 0x04,`
Line 186...	Line 194...
`uart_read (MSR, MSR_CTS \| MSR_DSR \| MSR_DCTS);`	`uart_read (MSR, MSR_CTS \| MSR_DSR \| MSR_DCTS);`
`uart_read (MSR, MSR_CTS \| MSR_DSR);`	`uart_read (MSR, MSR_CTS \| MSR_DSR);`
`uart_read (IIR, IIR_NONE);`	`uart_read (IIR, IIR_NONE);`
`uart_write (MCR, $MCR \| MCR_OUT1);`	`uart_write (MCR, $MCR \| MCR_OUT1);`
`uart_read (MCR, $MCR);`	`uart_read (MCR, $MCR);`
	`uart_read (MSR, MSR_CTS \| MSR_DSR \| MSR_RI);`
	`uart_read (IIR, IIR_NONE);`
`uart_write (MCR, $MCR & ~MCR_OUT1);`	`uart_write (MCR, $MCR & ~MCR_OUT1);`
`uart_read (MCR, $MCR);`	`uart_read (MCR, $MCR);`
`uart_read (IIR, IIR_MSRI);`	`uart_read (IIR, IIR_MSRI);`
`uart_read (MSR, MSR_CTS \| MSR_DSR \| MSR_TERI);`	`uart_read (MSR, MSR_CTS \| MSR_DSR \| MSR_TERI);`
`uart_read (IIR, IIR_NONE);`	`uart_read (IIR, IIR_NONE);`
Line 588...	Line 598...
`uart_read (LSR, LSR_THRE \| LSR_TEMT);`	`uart_read (LSR, LSR_THRE \| LSR_TEMT);`

`logmessage ("UART: FIFO test end");`	`logmessage ("UART: FIFO test end");`
`}`	`}`

	`sub uart_check_fifo64 ()`
	`{`
	`logmessage ("UART: Testing FIFO in 64 byte mode...");`
	`uart_write (IER, IER_ERBI \| IER_ETBEI \| IER_ELSI \| IER_EDSSI);`
	`uart_write (FCR, FCR_F64E \| FCR_FE \| FCR_RXFR \| FCR_TXFR);`
	`uart_read (IIR, IIR_THRI \| IIR_FE);`
	`uart_write (LCR, $LCR \| LCR_DLAB);`
	`uart_write (FCR, FCR_F64E \| FCR_FE);`
	`uart_write (LCR, $LCR & ~LCR_DLAB);`
	`uart_read (IIR, IIR_NONE \| IIR_FE \| IIR_F64E);`

	`uart_read (LSR, LSR_THRE \| LSR_TEMT);`
	`logmessage ("UART: Testing FIFO trigger level 1 byte...");`
	`uart_write (FCR, FCR_FE \| FCR_RT1);`
	`uart_read (IIR, IIR_NONE \| IIR_FE \| IIR_F64E);`
	`uart_send (1);`
	`uart_wait (4);`
	`uart_read (IIR, IIR_CTOI \| IIR_FE \| IIR_F64E);`
	`uart_read (LSR, LSR_DR \| LSR_THRE \| LSR_TEMT);`
	`uart_rrbr (0x00);`
	`uart_read (IIR, IIR_THRI \| IIR_FE \| IIR_F64E);`
	`uart_read (LSR, LSR_THRE \| LSR_TEMT);`
	`uart_read (IIR, IIR_NONE \| IIR_FE \| IIR_F64E);`

	`logmessage ("UART: Testing FIFO trigger level 16 byte...");`
	`uart_write (FCR, FCR_FE \| FCR_RT16);`
	`uart_send (15);`
	`uart_wait (15);`
	`uart_read (IIR, IIR_CTOI \| IIR_FE \| IIR_F64E);`
	`uart_read (LSR, LSR_DR \| LSR_THRE \| LSR_TEMT);`
	`uart_rrbr (0x00);`
	`uart_read (IIR, IIR_THRI \| IIR_FE \| IIR_F64E);`
	`uart_read (IIR, IIR_NONE \| IIR_FE \| IIR_F64E);`
	`uart_send (3);`
	`uart_wait (3);`
	`uart_read (IIR, IIR_RDAI \| IIR_FE \| IIR_F64E);`
	`uart_read (LSR, LSR_DR \| LSR_THRE \| LSR_TEMT);`
	`uart_rrbr (0x01);`
	`uart_read (IIR, IIR_RDAI \| IIR_FE \| IIR_F64E);`
	`uart_rrbr (0x02);`
	`uart_read (IIR, IIR_THRI \| IIR_FE \| IIR_F64E);`
	`uart_recv (12, 3);`
	`uart_recv (3);`
	`uart_read (LSR, LSR_THRE \| LSR_TEMT);`
	`uart_read (IIR, IIR_NONE \| IIR_FE \| IIR_F64E);`

	`logmessage ("UART: Testing FIFO trigger level 32 byte...");`
	`uart_write (FCR, FCR_FE \| FCR_RT32);`
	`uart_send (31);`
	`uart_wait (31);`
	`uart_read (IIR, IIR_CTOI \| IIR_FE \| IIR_F64E);`
	`uart_read (LSR, LSR_DR \| LSR_THRE \| LSR_TEMT);`
	`uart_rrbr (0x00);`
	`uart_read (IIR, IIR_THRI \| IIR_FE \| IIR_F64E);`
	`uart_read (IIR, IIR_NONE \| IIR_FE \| IIR_F64E);`
	`uart_send (3);`
	`uart_wait (3);`
	`uart_read (IIR, IIR_RDAI \| IIR_FE \| IIR_F64E);`
	`uart_read (LSR, LSR_DR \| LSR_THRE \| LSR_TEMT);`
	`uart_rrbr (0x01);`
	`uart_read (IIR, IIR_RDAI \| IIR_FE \| IIR_F64E);`
	`uart_rrbr (0x02);`
	`uart_read (IIR, IIR_THRI \| IIR_FE \| IIR_F64E);`
	`uart_recv (28, 3);`
	`uart_recv (3);`
	`uart_read (LSR, LSR_THRE \| LSR_TEMT);`
	`uart_read (IIR, IIR_NONE \| IIR_FE \| IIR_F64E);`

	`logmessage ("UART: Testing FIFO trigger level 56 byte...");`
	`uart_write (FCR, FCR_FE \| FCR_RT56);`
	`uart_send (55);`
	`uart_wait (55);`
	`uart_read (IIR, IIR_CTOI \| IIR_FE \| IIR_F64E);`
	`uart_read (LSR, LSR_DR \| LSR_THRE \| LSR_TEMT);`
	`uart_rrbr (0x00);`
	`uart_read (IIR, IIR_THRI \| IIR_FE \| IIR_F64E);`
	`uart_read (IIR, IIR_NONE \| IIR_FE \| IIR_F64E);`
	`uart_send (3);`
	`uart_wait (3);`
	`uart_read (IIR, IIR_RDAI \| IIR_FE \| IIR_F64E);`
	`uart_read (LSR, LSR_DR \| LSR_THRE \| LSR_TEMT);`
	`uart_rrbr (0x01);`
	`uart_read (IIR, IIR_RDAI \| IIR_FE \| IIR_F64E);`
	`uart_rrbr (0x02);`
	`uart_read (IIR, IIR_THRI \| IIR_FE \| IIR_F64E);`
	`uart_recv (52, 3);`
	`uart_recv (3);`
	`uart_read (LSR, LSR_THRE \| LSR_TEMT);`
	`uart_read (IIR, IIR_NONE \| IIR_FE \| IIR_F64E);`

	`uart_write (LCR, $LCR \| LCR_DLAB);`
	`uart_write (FCR, $FCR & ~FCR_F64E);`
	`uart_write (LCR, $LCR & ~LCR_DLAB);`
	`uart_read (IIR, IIR_NONE \| IIR_FE);`

	`logmessage ("UART: FIFO64 test end");`
	`}`

`sub uart_check_afc ()`	`sub uart_check_afc ()`
`{`	`{`
`logmessage ("UART: Automatic flow control test");`	`logmessage ("UART: Automatic flow control test");`
`uart_write (LCR, LCR_WLS8);`	`uart_write (LCR, LCR_WLS8);`
`uart_read (LCR, LCR_WLS8);`	`uart_read (LCR, LCR_WLS8);`
Line 672...	Line 780...
`uart_read (IIR, IIR_NONE \| IIR_FE);`	`uart_read (IIR, IIR_NONE \| IIR_FE);`
`uart_read (MCR, $MCR);`	`uart_read (MCR, $MCR);`
`logmessage ("UART: Automatic flow control test finished");`	`logmessage ("UART: Automatic flow control test finished");`
`}`	`}`

	`if (TEST_CONTROL) {`
`uart_check_control_lines ();`	`uart_check_control_lines ();`
	`}`
	`if (TEST_INTERRUPT) {`
`uart_check_interrupt_control ();`	`uart_check_interrupt_control ();`
	`}`
	`if (TEST_DEFAULT) {`
`uart_check_default ();`	`uart_check_default ();`
	`}`
	`if (TEST_FIFO) {`
`uart_check_fifo ();`	`uart_check_fifo ();`
	`}`
	`if (TEST_FIFO64) {`
	`uart_check_fifo64 ();`
	`}`
`if (TEST_AFC) {`	`if (TEST_AFC) {`
`uart_check_afc ();`	`uart_check_afc ();`
`}`	`}`

`##################################################################`	`##################################################################`

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[/] [uart16750/] [trunk/] [sim/] [rtl_sim/] [bin/] [uart_test_stim.pl] - Diff between revs 12 and 14