URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [scilab/] [calc_baud_gen.sce] - Diff between revs 2 and 7

Rev 2	Rev 7
Line 19...	Line 19...
`end`	`end`
`endfunction`	`endfunction`

`// request the required clock rate and baud rate parameters`	`// request the required clock rate and baud rate parameters`
`dig_labels = ["Clock Frequency in MHz"; "UART Baud Rate in bps"];`	`dig_labels = ["Clock Frequency in MHz"; "UART Baud Rate in bps"];`
`default_val = ["40", "115200"];`	`default_val = ["40"; "115200"];`
`params = evstr(x_mdialog("Enter Core Parameters", dig_labels, default_val));`	`params = evstr(x_mdialog("Enter Core Parameters", dig_labels, default_val));`

`// extract the parameters`	`// extract the parameters`
`global_clock_freq = params(1)*1e6;`	`global_clock_freq = params(1)*1e6;`
`baud_rate = params(2);`	`baud_rate = params(2);`
Line 44...	Line 44...
`""; ...`	`""; ...`
`"The verilog definition can be copied from the following lines:"; ...`	`"The verilog definition can be copied from the following lines:"; ...`
"`define D_BAUD_FREQ 12''d"+string(D_BAUD_FREQ); ...	"`define D_BAUD_FREQ 12''d"+string(D_BAUD_FREQ); ...
"`define D_BAUD_LIMIT 16''d"+string(D_BAUD_LIMIT);	"`define D_BAUD_LIMIT 16''d"+string(D_BAUD_LIMIT);
`];`	`];`
`x_message_modeless(mes_str);`	`messagebox(mes_str);`
`messagebox(mes_str);`	`messagebox(mes_str);`