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Line 135... |
wire [7:0] int_address; // address bus to register file
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wire [7:0] int_address; // address bus to register file
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wire [7:0] int_wr_data; // write data to register file
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wire [7:0] int_wr_data; // write data to register file
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wire int_write; // write control to register file
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wire int_write; // write control to register file
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wire int_read; // read control to register file
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wire int_read; // read control to register file
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wire [7:0] int_rd_data; // data read from register file
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wire [7:0] int_rd_data; // data read from register file
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wire int_req; // bus access request signal
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wire int_gnt; // bus access grant signal
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wire ser_in; // DUT serial input
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wire ser_in; // DUT serial input
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wire ser_out; // DUT serial output
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wire ser_out; // DUT serial output
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// DUT instance
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// DUT instance
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uart2bus_top uart2bus1
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uart2bus_top uart2bus1
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(
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(
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.clock(clock), .reset(reset),
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.clock(clock), .reset(reset),
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.ser_in(ser_in), .ser_out(ser_out),
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.ser_in(ser_in), .ser_out(ser_out),
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.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
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.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
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.int_rd_data(int_rd_data), .int_read(int_read)
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.int_rd_data(int_rd_data), .int_read(int_read),
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.int_req(int_req), .int_gnt(int_gnt)
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);
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);
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// bus grant is always active
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assign int_gnt = 1'b1;
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// serial interface to test bench
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// serial interface to test bench
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assign ser_in = serial_out;
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assign ser_in = serial_out;
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always @ (posedge clock) serial_in = ser_out;
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always @ (posedge clock) serial_in = ser_out;
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