| Line 9... |
Line 9... |
clock, reset,
|
clock, reset,
|
// uart serial signals
|
// uart serial signals
|
ser_in, ser_out,
|
ser_in, ser_out,
|
// internal bus to register file
|
// internal bus to register file
|
int_address, int_wr_data, int_write,
|
int_address, int_wr_data, int_write,
|
int_rd_data, int_read
|
int_rd_data, int_read,
|
|
int_req, int_gnt
|
);
|
);
|
//---------------------------------------------------------------------------------------
|
//---------------------------------------------------------------------------------------
|
// modules inputs and outputs
|
// modules inputs and outputs
|
input clock; // global clock input
|
input clock; // global clock input
|
input reset; // global reset input
|
input reset; // global reset input
|
| Line 22... |
Line 23... |
output [15:0] int_address; // address bus to register file
|
output [15:0] int_address; // address bus to register file
|
output [7:0] int_wr_data; // write data to register file
|
output [7:0] int_wr_data; // write data to register file
|
output int_write; // write control to register file
|
output int_write; // write control to register file
|
output int_read; // read control to register file
|
output int_read; // read control to register file
|
input [7:0] int_rd_data; // data read from register file
|
input [7:0] int_rd_data; // data read from register file
|
|
output int_req; // bus access request signal
|
|
input int_gnt; // bus access grant signal
|
|
|
// baud rate configuration, see baud_gen.v for more details.
|
// baud rate configuration, see baud_gen.v for more details.
|
// baud rate generator parameters for 115200 baud on 40MHz clock
|
// baud rate generator parameters for 115200 baud on 40MHz clock
|
`define D_BAUD_FREQ 12'h90
|
`define D_BAUD_FREQ 12'h90
|
`define D_BAUD_LIMIT 16'h0ba5
|
`define D_BAUD_LIMIT 16'h0ba5
|
| Line 68... |
Line 71... |
(
|
(
|
.clock(clock), .reset(reset),
|
.clock(clock), .reset(reset),
|
.rx_data(rx_data), .new_rx_data(new_rx_data),
|
.rx_data(rx_data), .new_rx_data(new_rx_data),
|
.tx_data(tx_data), .new_tx_data(new_tx_data), .tx_busy(tx_busy),
|
.tx_data(tx_data), .new_tx_data(new_tx_data), .tx_busy(tx_busy),
|
.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
|
.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
|
.int_rd_data(int_rd_data), .int_read(int_read)
|
.int_rd_data(int_rd_data), .int_read(int_read),
|
|
.int_req(int_req), .int_gnt(int_gnt)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
//---------------------------------------------------------------------------------------
|
//---------------------------------------------------------------------------------------
|
// Th.. Th.. Th.. Thats all folks !!!
|
// Th.. Th.. Th.. Thats all folks !!!
|
