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Line 10... |
// transmit and receive internal interface signals from uart interface
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// transmit and receive internal interface signals from uart interface
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rx_data, new_rx_data,
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rx_data, new_rx_data,
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tx_data, new_tx_data, tx_busy,
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tx_data, new_tx_data, tx_busy,
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// internal bus to register file
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// internal bus to register file
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int_address, int_wr_data, int_write,
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int_address, int_wr_data, int_write,
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int_rd_data, int_read
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int_rd_data, int_read,
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int_req, int_gnt
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);
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);
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// parameters
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// parameters
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parameter AW = 8; // address bus width parameter
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parameter AW = 8; // address bus width parameter
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Line 31... |
output [AW-1:0] int_address; // address bus to register file
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output [AW-1:0] int_address; // address bus to register file
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output [7:0] int_wr_data; // write data to register file
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output [7:0] int_wr_data; // write data to register file
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output int_write; // write control to register file
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output int_write; // write control to register file
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output int_read; // read control to register file
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output int_read; // read control to register file
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input [7:0] int_rd_data; // data read from register file
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input [7:0] int_rd_data; // data read from register file
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output int_req; // bus access request signal
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input int_gnt; // bus access grant signal
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// registered outputs
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// registered outputs
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reg [7:0] tx_data;
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reg [7:0] tx_data;
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reg new_tx_data;
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reg new_tx_data;
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reg [AW-1:0] int_address;
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reg [AW-1:0] int_address;
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reg [7:0] int_wr_data;
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reg [7:0] int_wr_data;
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reg int_write, int_read;
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reg write_req, read_req, int_write, int_read;
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// internal constants
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// internal constants
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// define characters used by the parser
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// define characters used by the parser
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`define CHAR_CR 8'h0d
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`define CHAR_CR 8'h0d
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`define CHAR_LF 8'h0a
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`define CHAR_LF 8'h0a
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Line 404... |
// internal write control and data
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// internal write control and data
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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write_req <= 1'b0;
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int_write <= 1'b0;
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int_write <= 1'b0;
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int_wr_data <= 0;
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int_wr_data <= 0;
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end
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end
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else if (write_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
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else if (write_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
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begin
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begin
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int_write <= 1'b1;
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write_req <= 1'b1;
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int_wr_data <= data_param;
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int_wr_data <= data_param;
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end
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end
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// binary extension mode
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// binary extension mode
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else if (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)
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else if (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)
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begin
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begin
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int_write <= 1'b1;
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write_req <= 1'b1;
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int_wr_data <= rx_data;
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int_wr_data <= rx_data;
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end
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end
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else if (int_gnt && write_req)
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begin
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// set internal bus write and clear the write request flag
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int_write <= 1'b1;
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write_req <= 1'b0;
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end
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else
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else
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int_write <= 1'b0;
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int_write <= 1'b0;
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end
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end
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// internal read control
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// internal read control
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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int_read <= 1'b0;
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int_read <= 1'b0;
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read_req <= 1'b0;
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end
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else if (read_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
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else if (read_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
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int_read <= 1'b1;
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read_req <= 1'b1;
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// binary extension
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// binary extension
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else if (bin_read_op && (main_sm == `MAIN_BIN_LEN) && new_rx_data)
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else if (bin_read_op && (main_sm == `MAIN_BIN_LEN) && new_rx_data)
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// the first read request is issued on reception of the length byte
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// the first read request is issued on reception of the length byte
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int_read <= 1'b1;
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read_req <= 1'b1;
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else if (bin_read_op && tx_end_p && !bin_last_byte)
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else if (bin_read_op && tx_end_p && !bin_last_byte)
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// the next read requests are issued after the previous read value was transmitted and
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// the next read requests are issued after the previous read value was transmitted and
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// this is not the last byte to be read.
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// this is not the last byte to be read.
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read_req <= 1'b1;
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else if (int_gnt && read_req)
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begin
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// set internal bus read and clear the read request flag
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int_read <= 1'b1;
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int_read <= 1'b1;
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read_req <= 1'b0;
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end
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else
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else
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int_read <= 1'b0;
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int_read <= 1'b0;
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end
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end
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// external request signal is active on read or write request
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assign int_req = write_req | read_req;
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// internal address
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// internal address
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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int_address <= 0;
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int_address <= 0;
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Line 451... |
Line 473... |
else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
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else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
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// sample address parameter on reception of length byte
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// sample address parameter on reception of length byte
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int_address <= addr_param[AW-1:0];
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int_address <= addr_param[AW-1:0];
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else if (addr_auto_inc &&
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else if (addr_auto_inc &&
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((bin_read_op && tx_end_p && !bin_last_byte) ||
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((bin_read_op && tx_end_p && !bin_last_byte) ||
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// (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)))
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(bin_write_op && int_write)))
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(bin_write_op && int_write)))
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// address is incremented on every read or write if enabled
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// address is incremented on every read or write if enabled
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int_address <= int_address + 1;
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int_address <= int_address + 1;
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end
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end
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