URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_tx.v] - Diff between revs 2 and 9

Rev 2	Rev 9
Line 49...	Line 49...
`begin`	`begin`
`if (reset)`	`if (reset)`
`tx_busy <= 1'b0;`	`tx_busy <= 1'b0;`
`else if (~tx_busy & new_tx_data)`	`else if (~tx_busy & new_tx_data)`
`tx_busy <= 1'b1;`	`tx_busy <= 1'b1;`
`else if (tx_busy & (bit_count == 4'ha) & ce_1)`	`else if (tx_busy & (bit_count == 4'h9) & ce_1)`
`tx_busy <= 1'b0;`	`tx_busy <= 1'b0;`
`end`	`end`

`// output bit counter`	`// output bit counter`
`always @ (posedge clock or posedge reset)`	`always @ (posedge clock or posedge reset)`