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[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [baudGen.vhd] - Diff between revs 11 and 13
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| Rev 11 |
Rev 13 |
| Line 9... |
Line 9... |
-- baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
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-- baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
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--
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--
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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity baudGen is
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entity baudGen is
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port ( clr : in std_logic; -- global reset input
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port ( clr : in std_logic; -- global reset input
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clk : in std_logic; -- global clock input
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clk : in std_logic; -- global clock input
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-- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
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-- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
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| Line 35... |
Line 35... |
if (clr = '1') then
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if (clr = '1') then
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counter <= (others => '0');
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counter <= (others => '0');
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ce16 <= '0';
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ce16 <= '0';
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if (counter >= baudLimit) then
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if (counter >= baudLimit) then
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counter <= counter - baudLimit;
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counter <= std_logic_vector(unsigned(counter) - unsigned(baudLimit));
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ce16 <= '1';
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ce16 <= '1';
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else
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else
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counter <= counter + baudFreq;
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counter <= std_logic_vector(unsigned(counter) + unsigned(baudFreq));
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ce16 <= '0';
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ce16 <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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