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-- uart parser module
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-- uart parser module
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--
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--
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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.ALL;
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use ieee.std_logic_unsigned.ALL;
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use ieee.numeric_std.ALL;
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entity uartParser is
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entity uartParser is
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generic ( -- parameters
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generic ( -- parameters
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AW : integer := 8);
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AW : integer := 8);
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port ( -- global signals
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port ( -- global signals
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Line 349... |
if ((mainSm = mainBinLen) and (newRxData = '1')) then
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if ((mainSm = mainBinLen) and (newRxData = '1')) then
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binByteCount <= rxData;
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binByteCount <= rxData;
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elsif (((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) or ((binReadOp = '1') and (txEndP = '1'))) then
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elsif (((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) or ((binReadOp = '1') and (txEndP = '1'))) then
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-- byte counter is updated on every new data received in write operations and for every
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-- byte counter is updated on every new data received in write operations and for every
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-- byte transmitted for read operations.
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-- byte transmitted for read operations.
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binByteCount <= binByteCount - 1;
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binByteCount <= std_logic_vector(unsigned(binByteCount) - 1);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- internal write control and data
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-- internal write control and data
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-- internal read control
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-- internal read control
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elsif ((mainSm = mainBinLen) and (newRxData = '1')) then
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elsif ((mainSm = mainBinLen) and (newRxData = '1')) then
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-- sample address parameter on reception of length byte
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-- sample address parameter on reception of length byte
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iIntAddress <= addrParam(AW - 1 downto 0);
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iIntAddress <= addrParam(AW - 1 downto 0);
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elsif ((addrAutoInc = '1') and (((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) or ((binWriteOp = '1') and (iIntWrite = '1')))) then
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elsif ((addrAutoInc = '1') and (((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) or ((binWriteOp = '1') and (iIntWrite = '1')))) then
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-- address is incremented on every read or write if enabled
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-- address is incremented on every read or write if enabled
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iIntAddress <= iIntAddress + 1;
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iIntAddress <= std_logic_vector(unsigned(iIntAddress) + 1);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- read done flag and sampled data read
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-- read done flag and sampled data read
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process (clr, clk)
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process (clr, clk)
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