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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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-- uart parser module
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-- uart parser module
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--
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--
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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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library IEEE;
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.std_logic_unsigned.ALL;
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entity uartParser is
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entity uartParser is
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generic ( -- parameters
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generic ( -- parameters
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AW : integer := 8);
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AW : integer := 8);
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port ( -- global signals
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port ( -- global signals
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rxData : in std_logic_vector(7 downto 0); -- data byte received
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rxData : in std_logic_vector(7 downto 0); -- data byte received
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newRxData : in std_logic; -- signs that a new byte was received
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newRxData : in std_logic; -- signs that a new byte was received
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txData : out std_logic_vector(7 downto 0); -- data byte to transmit
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txData : out std_logic_vector(7 downto 0); -- data byte to transmit
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newTxData : out std_logic; -- asserted to indicate that there is a new data byte for transmission
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newTxData : out std_logic; -- asserted to indicate that there is a new data byte for transmission
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-- internal bus to register file
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-- internal bus to register file
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intReq : out std_logic; --
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intGnt : in std_logic; --
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intRdData : in std_logic_vector(7 downto 0); -- data read from register file
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intRdData : in std_logic_vector(7 downto 0); -- data read from register file
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intAddress : out std_logic_vector(AW - 1 downto 0); -- address bus to register file
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intAddress : out std_logic_vector(AW - 1 downto 0); -- address bus to register file
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intWrData : out std_logic_vector(7 downto 0); -- write data to register file
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intWrData : out std_logic_vector(7 downto 0); -- write data to register file
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intWrite : out std_logic; -- write control to register file
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intWrite : out std_logic; -- write control to register file
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intRead : out std_logic); -- read control to register file
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intRead : out std_logic); -- read control to register file
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signal dataNibble : std_logic_vector(3 downto 0); -- data nibble from received character
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signal dataNibble : std_logic_vector(3 downto 0); -- data nibble from received character
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signal addrParam : std_logic_vector(15 downto 0); -- operation address parameter
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signal addrParam : std_logic_vector(15 downto 0); -- operation address parameter
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signal addrNibble : std_logic_vector(3 downto 0); -- data nibble from received character
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signal addrNibble : std_logic_vector(3 downto 0); -- data nibble from received character
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signal binByteCount : std_logic_vector(7 downto 0); -- binary mode byte counter
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signal binByteCount : std_logic_vector(7 downto 0); -- binary mode byte counter
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signal iIntAddress : std_logic_vector(intAddress'range); --
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signal iIntAddress : std_logic_vector(intAddress'range); --
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signal iWriteReq : std_logic; --
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signal iIntWrite : std_logic; --
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signal iIntWrite : std_logic; --
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signal readDone : std_logic; -- internally generated read done flag
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signal readDone : std_logic; -- internally generated read done flag
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signal readDoneS : std_logic; -- sampled read done
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signal readDoneS : std_logic; -- sampled read done
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signal readDataS : std_logic_vector(7 downto 0); -- sampled read data
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signal readDataS : std_logic_vector(7 downto 0); -- sampled read data
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signal iReadReq : std_logic; --
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signal iIntRead : std_logic; --
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signal iIntRead : std_logic; --
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signal txChar : std_logic_vector(7 downto 0); -- transmit byte from nibble to character conversion
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signal txChar : std_logic_vector(7 downto 0); -- transmit byte from nibble to character conversion
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signal sTxBusy : std_logic; -- sampled tx_busy for falling edge detection
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signal sTxBusy : std_logic; -- sampled tx_busy for falling edge detection
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signal txNibble : std_logic_vector(3 downto 0); -- nibble value for transmission
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signal txNibble : std_logic_vector(3 downto 0); -- nibble value for transmission
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-- internal write control and data
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-- internal write control and data
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-- internal read control
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-- internal read control
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process (clr, clk)
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process (clr, clk)
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begin
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begin
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if (clr = '1') then
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if (clr = '1') then
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iReadReq <= '0';
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iIntRead <= '0';
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iIntRead <= '0';
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iWriteReq <= '0';
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iIntWrite <= '0';
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iIntWrite <= '0';
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intWrData <= (others => '0');
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intWrData <= (others => '0');
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if ((mainSm = mainAddr) and (writeOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
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if ((mainSm = mainAddr) and (writeOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
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iIntWrite <= '1';
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iWriteReq <= '1';
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intWrData <= dataParam;
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intWrData <= dataParam;
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-- binary extension mode
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-- binary extension mode
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elsif ((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) then
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elsif ((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) then
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iIntWrite <= '1';
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iWriteReq <= '1';
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intWrData <= rxData;
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intWrData <= rxData;
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elsif ((intGnt = '1') and (iWriteReq = '1')) then
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iWriteReq <= '0';
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iIntWrite <= '1';
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else
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else
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iIntWrite <= '0';
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iIntWrite <= '0';
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end if;
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end if;
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if ((mainSm = mainAddr) and (readOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
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if ((mainSm = mainAddr) and (readOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
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iIntRead <= '1';
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iReadReq <= '1';
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-- binary extension
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-- binary extension
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elsif ((mainSm = mainBinLen) and (binReadOp = '1') and (newRxData = '1')) then
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elsif ((mainSm = mainBinLen) and (binReadOp = '1') and (newRxData = '1')) then
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-- the first read request is issued on reception of the length byte
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-- the first read request is issued on reception of the length byte
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iIntRead <= '1';
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iReadReq <= '1';
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elsif ((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) then
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elsif ((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) then
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-- the next read requests are issued after the previous read value was transmitted and
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-- the next read requests are issued after the previous read value was transmitted and
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-- this is not the last byte to be read.
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-- this is not the last byte to be read.
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iReadReq <= '1';
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elsif ((intGnt = '1') and (iReadReq = '1')) then
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iReadReq <= '0';
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iIntRead <= '1';
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iIntRead <= '1';
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else
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else
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iIntRead <= '0';
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iIntRead <= '0';
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end if;
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end if;
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end if;
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end if;
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charFHigh when x"F",
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charFHigh when x"F",
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charFHigh when others;
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charFHigh when others;
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intAddress <= iIntAddress;
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intAddress <= iIntAddress;
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intWrite <= iIntWrite;
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intWrite <= iIntWrite;
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intRead <= iIntRead;
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intRead <= iIntRead;
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intReq <= '1' when (iReadReq = '1') else
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'1' when (iWriteReq = '1') else '0';
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end Behavioral;
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end Behavioral;
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