URL
https://opencores.org/ocsvn/uart2bus/uart2bus/trunk
[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [uartRx.vhd] - Diff between revs 6 and 10
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 6 |
Rev 10 |
Line 58... |
Line 58... |
if (clr = '1') then
|
if (clr = '1') then
|
rxBusy <= '0';
|
rxBusy <= '0';
|
elsif (rising_edge(clk)) then
|
elsif (rising_edge(clk)) then
|
if ((rxBusy = '0') and (ce1Mid = '1')) then
|
if ((rxBusy = '0') and (ce1Mid = '1')) then
|
rxBusy <= '1';
|
rxBusy <= '1';
|
elsif ((rxBusy = '1') and (bitCount = "1001") and (ce1 = '1')) then
|
elsif ((rxBusy = '1') and (bitCount = "1000") and (ce1 = '1')) then
|
rxBusy <= '0';
|
rxBusy <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
-- bit counter
|
-- bit counter
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.