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[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [uartTop.vhd] - Diff between revs 6 and 11
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-- uart top level module
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-- uart top level module
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--
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--
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library IEEE;
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_1164.all;
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library work;
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use work.uart2BusTop_pkg.all;
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entity uartTop is
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entity uartTop is
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port ( -- global signals
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port ( -- global signals
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clr : in std_logic; -- global reset input
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clr : in std_logic; -- global reset input
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clk : in std_logic; -- global clock input
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clk : in std_logic; -- global clock input
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baudClk : out std_logic); --
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baudClk : out std_logic); --
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end uartTop;
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end uartTop;
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architecture Behavioral of uartTop is
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architecture Behavioral of uartTop is
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component baudGen
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port (
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clr : in std_logic;
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clk : in std_logic;
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baudFreq : in std_logic_vector(11 downto 0);
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baudLimit : in std_logic_vector(15 downto 0);
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ce16 : out std_logic);
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end component;
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component uartTx
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port (
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clr : in std_logic;
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clk : in std_logic;
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ce16 : in std_logic;
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txData : in std_logic_vector(7 downto 0);
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newTxData : in std_logic;
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serOut : out std_logic;
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txBusy : out std_logic);
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end component;
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component uartRx
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port (
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clr : in std_logic;
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clk : in std_logic;
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ce16 : in std_logic;
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serIn : in std_logic;
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rxData : out std_logic_vector(7 downto 0);
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newRxData : out std_logic);
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end component;
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signal ce16 : std_logic; -- clock enable at bit rate
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signal ce16 : std_logic; -- clock enable at bit rate
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begin
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begin
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-- baud rate generator module
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-- baud rate generator module
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bg : baudGen
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bg : baudGen
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