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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// UART2BUS VERIFICATION
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// UART2BUS VERIFICATION
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//
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//
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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------// CREATOR : HANY SALAH
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : CONFIGURATION
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// UNIT : AGENT
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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------// TITLE : UART Configuration
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// TITLE : UART Configuration
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// DESCRIPTION: UART Configuration INCLUDES INSTANCE OF THE THREE BFMS. ALSO INCLUDES THE WHOLE EN-
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// DESCRIPTION: This
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// VIRONMENT CONFIGURATIONS THAT ARE SET IN THE TEST.
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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------// LOG DETAILS
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// LOG DETAILS
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//-------------
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 02012016 FILE CREATION
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// 1 HANY SALAH 02012016 FILE CREATION
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//-----------------------------------------------------------------------------
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// 2 HANY SALAH 09022016 REFINE THE BLOCK DESCRIPTION AND ADD DESCRIPTIVE COMMENTS
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
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//-------------------------------------------------------------------------------------------------// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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// CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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class uart_config extends uvm_object;
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class uart_config extends uvm_object;
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// Uart BFM Instance
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virtual uart_interface uart_inf;
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virtual uart_interface uart_inf;
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// Register File BFM Instance
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virtual rf_interface rf_inf;
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virtual rf_interface rf_inf;
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// Arbiter BFM Instance
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virtual uart_arbiter arb_inf;
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virtual uart_arbiter arb_inf;
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// Active clock edge that would syncronize the whole system to be either the positive or the neg-
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// tive edge
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act_edge _edge;
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act_edge _edge;
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// Define the sequence to be used in transmitting one byte serially; either to start with the MSB
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// or the LSB.
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start_bit _start;
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start_bit _start;
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// Define the Represenetation of data through the text mode to be either ASCII or Binary
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data_mode _datamode;
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data_mode _datamode;
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// Define the number of stop bits at the final of each UART field to be one of two bits
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int num_stop_bits;
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int num_stop_bits;
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// Define the number of bits inbetween the start and the stop bits to be seven or eight bits
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int num_of_bits;
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int num_of_bits;
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// Define the parity mode used to be either no parity, odd parity or even parity.
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parity_mode _paritymode;
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parity_mode _paritymode;
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// Define the maximum time between the generated stimulus and the DUT response.
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time response_time;
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time response_time;
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// Define the possibility of generating false data through the read command. This attribute is
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// general control one that would be make this feature would be used or not. And another field
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// would be generated through the sequence.
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req use_false_data;
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`uvm_object_utils(uart_config)
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`uvm_object_utils(uart_config)
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function new (string name = "uart_config");
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function new (string name = "uart_config");
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super.new(name);
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super.new(name);
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endfunction:new
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endfunction:new
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