| Line 1... |
Line 1... |
//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// UART2BUS VERIFICATION
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// UART2BUS VERIFICATION
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//
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//
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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// CREATOR : HANY SALAH
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : SEQUENCE
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// UNIT : SEQUENCE
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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// TITLE : UART Sequence
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// TITLE : UART SEQUENCE
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// DESCRIPTION: This
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// DESCRIPTION: THIS FILE INCLUDES THE ALL SEQUENCES THAT WOULD BE FORCED INTO DUT. THE SEQUENCES
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//-----------------------------------------------------------------------------
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// MENTIONED BELOW IS IDENTIFIED IN THE MANNER RELATED TO THE TEST PLAN SECTION IN
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// THE DOCUMENT; IT IS IDENTIFIED USING TWO TERMS; SUBSECTION AND ITEM INSIDE SUB-
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// SECTION.
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//-------------------------------------------------------------------------------------------------
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// LOG DETAILS
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// LOG DETAILS
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//-------------
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 01012016 FILE CREATION
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// 1 HANY SALAH 01012016 FILE CREATION
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// 2 HANY SALAH 02012016 ADD REST OF TESTS
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// 2 HANY SALAH 02012016 ADD REST OF TESTS
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//-----------------------------------------------------------------------------
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// 3 HANY SALAH 29012016 INSERT WRONG MODE IN BOTH BINARY AND TEXT COMMUNICATION
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
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// MODES
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// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
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// 4 HANY SALAH 09022016 REFINE BLOCK DESCRIPTION
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// CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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// Base Sequence Class that hold the common attributes to all sequences
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// Base Sequence Class that hold the common attributes to all sequences
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class uart_base_sequence extends uvm_sequence #(uart_transaction);
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class uart_base_sequence extends uvm_sequence #(uart_transaction);
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|
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uart_transaction trans;
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uart_transaction trans;
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| Line 33... |
Line 37... |
super.new(name);
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super.new(name);
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trans = uart_transaction::type_id::create("trans");
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trans = uart_transaction::type_id::create("trans");
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endfunction:new
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endfunction:new
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endclass:uart_base_sequence
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endclass:uart_base_sequence
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//-------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// WRITE IN TEXT MODE
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// WRITE IN TEXT MODE
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//
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//
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//-------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// 1.1 Apply UART write request using capital W
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// 1.1 Apply UART write request using capital W
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class seq_1p1 extends uart_base_sequence;
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class seq_1p1 extends uart_base_sequence;
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|
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`uvm_object_utils(seq_1p1)
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`uvm_object_utils(seq_1p1)
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| Line 269... |
Line 273... |
_spacetype1 != wrong_space;
|
_spacetype1 != wrong_space;
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_spacetype2 != wrong_space;
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_spacetype2 != wrong_space;
|
length_data == 1;
|
length_data == 1;
|
_eoltype != wrong_eol;
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_eoltype != wrong_eol;
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_command == write;
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_command == write;
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address == 4'hFFFF;
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address == 16'hFFFF;
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_reqinc == no;
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_reqinc == no;
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_arbit == accept;
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_arbit == accept;
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};
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};
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finish_item(trans);
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finish_item(trans);
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endtask:body
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endtask:body
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| Line 323... |
Line 327... |
_spacetype1 != wrong_space;
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_spacetype1 != wrong_space;
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_spacetype2 != wrong_space;
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_spacetype2 != wrong_space;
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length_data == 1;
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length_data == 1;
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_eoltype != wrong_eol;
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_eoltype != wrong_eol;
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_command == write;
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_command == write;
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_data [0] == 2'hff;
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_data [0] == 8'hff;
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_reqinc == no;
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_reqinc == no;
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_arbit == accept;
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_arbit == accept;
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} ;
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} ;
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finish_item(trans);
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finish_item(trans);
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endtask:body
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endtask:body
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endclass:seq_1p11
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endclass:seq_1p11
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//-------------------------------------------------------
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// 1.12 Apply UART write request using different EOL character.
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class seq_1p12 extends uart_base_sequence;
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`uvm_object_utils(seq_1p12)
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function new (string name = "seq_1p12");
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super.new(name);
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endfunction:new
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virtual task body ();
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start_item(trans);
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trans.randomize() with {
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_mode == text;
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_spacetype1 != wrong_space;
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_spacetype2 != wrong_space;
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length_data == 1;
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_eoltype == wrong_eol;
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_command == write;
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_reqinc == no;
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_arbit == accept;
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} ;
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finish_item(trans);
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endtask:body
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endclass:seq_1p12
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// 1.13 Apply UART Write request using wrong prefix
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class seq_1p13 extends uart_base_sequence;
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`uvm_object_utils(seq_1p13)
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function new (string name = "seq_1p13");
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super.new(name);
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endfunction:new
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virtual task body ();
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start_item(trans);
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trans.randomize() with {
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_mode == wrong_mode_text;
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_spacetype1 != wrong_space;
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_spacetype2 != wrong_space;
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length_data == 1;
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_eoltype != wrong_eol;
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_command == write;
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_reqinc == no;
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_arbit == accept;
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} ;
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finish_item(trans);
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endtask:body
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endclass:seq_1p13
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//-------------------------------------------------------------------------------------------------
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//
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//
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// READ IN TEXT MODE
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// READ IN TEXT MODE
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//
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//
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//-------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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|
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// 2.1 Apply UART read request using capital R
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// 2.1 Apply UART read request using capital R
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class seq_2p1 extends uart_base_sequence;
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class seq_2p1 extends uart_base_sequence;
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`uvm_object_utils(seq_2p1)
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`uvm_object_utils(seq_2p1)
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| Line 568... |
Line 623... |
_spacetype1 != wrong_space;
|
_spacetype1 != wrong_space;
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_spacetype2 != wrong_space;
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_spacetype2 != wrong_space;
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length_data == 1;
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length_data == 1;
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_eoltype != wrong_eol;
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_eoltype != wrong_eol;
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_command == read;
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_command == read;
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address == 4'hFFFF;
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address == 16'hFFFF;
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_reqinc == no;
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_reqinc == no;
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_arbit == accept;
|
_arbit == accept;
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} ;
|
} ;
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finish_item(trans);
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finish_item(trans);
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endtask:body
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endtask:body
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| Line 622... |
Line 677... |
_spacetype1 != wrong_space;
|
_spacetype1 != wrong_space;
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_spacetype2 != wrong_space;
|
_spacetype2 != wrong_space;
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length_data == 1;
|
length_data == 1;
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_eoltype != wrong_eol;
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_eoltype != wrong_eol;
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_command == read;
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_command == read;
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_data [0] == 2'hff;
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_data [0] == 8'hff;
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_reqinc == no;
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_reqinc == no;
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_arbit == accept;
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_arbit == accept;
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} ;
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} ;
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finish_item(trans);
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finish_item(trans);
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endtask:body
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endtask:body
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endclass:seq_2p11
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endclass:seq_2p11
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//-------------------------------------------------------
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|
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// 2.12 Apply UART read request using different EOL character.
|
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class seq_2p12 extends uart_base_sequence;
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|
|
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`uvm_object_utils(seq_2p12)
|
|
|
|
function new (string name = "seq_2p12");
|
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super.new(name);
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endfunction:new
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|
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virtual task body ();
|
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start_item(trans);
|
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trans.randomize() with {
|
|
_mode == text;
|
|
_spacetype1 != wrong_space;
|
|
_spacetype2 != wrong_space;
|
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length_data == 1;
|
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_eoltype == wrong_eol;
|
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_command == read;
|
|
_reqinc == no;
|
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_arbit == accept;
|
|
} ;
|
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finish_item(trans);
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endtask:body
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endclass:seq_2p12
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|
|
|
|
|
// 2.13 Apply UART Read request using wrong prefix
|
|
class seq_2p13 extends uart_base_sequence;
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|
|
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`uvm_object_utils(seq_2p13)
|
|
|
|
function new (string name = "seq_2p13");
|
|
super.new(name);
|
|
endfunction:new
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|
|
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virtual task body ();
|
|
start_item(trans);
|
|
trans.randomize() with {
|
|
_mode == wrong_mode_text;
|
|
_spacetype1 != wrong_space;
|
|
_spacetype2 != wrong_space;
|
|
length_data == 1;
|
|
_eoltype != wrong_eol;
|
|
_command == read;
|
|
_reqinc == no;
|
|
_arbit == accept;
|
|
} ;
|
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finish_item(trans);
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endtask:body
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endclass:seq_2p13
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|
|
|
//-------------------------------------------------------------------------------------------------
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//
|
//
|
// NOP IN COMMAND MODE
|
// NOP IN COMMAND MODE
|
//
|
//
|
//-------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
|
|
// 3.1 Apply UART NOP command with acknowledge request and right command
|
// 3.1 Apply UART NOP command with acknowledge request and right command
|
// mode prefix
|
// mode prefix
|
class seq_3p1 extends uart_base_sequence;
|
class seq_3p1 extends uart_base_sequence;
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|
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| Line 655... |
Line 762... |
_command == nop;
|
_command == nop;
|
(length_data > 1) -> (_reqinc == yes);
|
(length_data > 1) -> (_reqinc == yes);
|
_arbit == accept;
|
_arbit == accept;
|
_reqack == yes;
|
_reqack == yes;
|
} ;
|
} ;
|
|
$display("reached here sequence @time=%0t ,, _mode = %p",$time,trans._mode);
|
finish_item(trans);
|
finish_item(trans);
|
endtask:body
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endtask:body
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endclass:seq_3p1
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endclass:seq_3p1
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|
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// 3.2 Apply UART NOP command with acknowledge request and wrong command
|
// 3.2 Apply UART NOP command with acknowledge request and wrong command
|
| Line 672... |
Line 780... |
endfunction:new
|
endfunction:new
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|
|
virtual task body ();
|
virtual task body ();
|
start_item(trans);
|
start_item(trans);
|
trans.randomize() with {
|
trans.randomize() with {
|
_mode == wrong_mode;
|
_mode == wrong_mode_bin;
|
_command == nop;
|
_command == nop;
|
address[15:7] != 2'h00;
|
address != 16'h0;
|
(length_data > 1) -> (_reqinc == yes);
|
(length_data > 1) -> (_reqinc == yes);
|
_arbit == accept;
|
_arbit == accept;
|
_reqack == yes;
|
_reqack == yes;
|
} ;
|
} ;
|
finish_item(trans);
|
finish_item(trans);
|
| Line 752... |
Line 860... |
endfunction:new
|
endfunction:new
|
|
|
virtual task body ();
|
virtual task body ();
|
start_item(trans);
|
start_item(trans);
|
trans.randomize() with {
|
trans.randomize() with {
|
_mode == wrong_mode;
|
_mode == wrong_mode_bin;
|
_command == nop;
|
_command == nop;
|
address[15:7] != 2'h00;
|
address[15:7] != 8'h00;
|
(length_data > 1) -> (_reqinc == yes);
|
(length_data > 1) -> (_reqinc == yes);
|
_arbit == accept;
|
_arbit == accept;
|
_reqack == no;
|
_reqack == no;
|
} ;
|
} ;
|
finish_item(trans);
|
finish_item(trans);
|
| Line 796... |
Line 904... |
end
|
end
|
finish_item(trans);
|
finish_item(trans);
|
endtask:body
|
endtask:body
|
endclass:seq_4p3
|
endclass:seq_4p3
|
|
|
//-------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
//
|
//
|
// WRITE IN COMMAND MODE
|
// WRITE IN COMMAND MODE
|
//
|
//
|
//-------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
|
|
// 5.1 Apply UART write command with wrong prefix.
|
// 5.1 Apply UART write command with wrong prefix.
|
class seq_5p1 extends uart_base_sequence;
|
class seq_5p1 extends uart_base_sequence;
|
|
|
`uvm_object_utils(seq_5p1)
|
`uvm_object_utils(seq_5p1)
|
| Line 814... |
Line 922... |
endfunction:new
|
endfunction:new
|
|
|
virtual task body ();
|
virtual task body ();
|
start_item(trans);
|
start_item(trans);
|
trans.randomize() with {
|
trans.randomize() with {
|
_mode == wrong_mode;
|
_mode == wrong_mode_bin;
|
_command == write;
|
_command == write;
|
address[15:7] != 2'h00;
|
address[15:7] != 8'h00;
|
(length_data > 1) -> (_reqinc == yes);
|
(length_data > 1) -> (_reqinc == yes);
|
_arbit == accept;
|
_arbit == accept;
|
} ;
|
} ;
|
finish_item(trans);
|
finish_item(trans);
|
endtask:body
|
endtask:body
|
| Line 922... |
Line 1030... |
virtual task body ();
|
virtual task body ();
|
start_item(trans);
|
start_item(trans);
|
trans.randomize() with {
|
trans.randomize() with {
|
_mode == binary;
|
_mode == binary;
|
_command == write;
|
_command == write;
|
address == 4'hffff;
|
address == 16'hFFFF;
|
(length_data > 1) -> (_reqinc == yes);
|
(length_data > 1) -> (_reqinc == yes);
|
_arbit == accept;
|
_arbit == accept;
|
} ;
|
} ;
|
finish_item(trans);
|
finish_item(trans);
|
endtask:body
|
endtask:body
|
| Line 1040... |
Line 1148... |
} ;
|
} ;
|
finish_item(trans);
|
finish_item(trans);
|
endtask:body
|
endtask:body
|
endclass:seq_5p10
|
endclass:seq_5p10
|
|
|
|
//-------------------------------------------------------------------------------------------------
|
//-------------------------------------------------------
|
|
//
|
//
|
// READ IN COMMAND MODE
|
// READ IN COMMAND MODE
|
//
|
//
|
//-------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
|
|
// 6.1 Apply UART read command with wrong prefix.
|
// 6.1 Apply UART read command with wrong prefix.
|
class seq_6p1 extends uart_base_sequence;
|
class seq_6p1 extends uart_base_sequence;
|
|
|
`uvm_object_utils(seq_6p1)
|
`uvm_object_utils(seq_6p1)
|
| Line 1059... |
Line 1166... |
endfunction:new
|
endfunction:new
|
|
|
virtual task body ();
|
virtual task body ();
|
start_item(trans);
|
start_item(trans);
|
trans.randomize() with {
|
trans.randomize() with {
|
_mode == wrong_mode;
|
_mode == wrong_mode_bin;
|
_command == read;
|
_command == read;
|
address[15:7] != 2'h00;
|
address[15:7] != 8'h00;
|
(length_data > 1) -> (_reqinc == yes);
|
(length_data > 1) -> (_reqinc == yes);
|
_arbit == accept;
|
_arbit == accept;
|
} ;
|
} ;
|
finish_item(trans);
|
finish_item(trans);
|
endtask:body
|
endtask:body
|
| Line 1167... |
Line 1274... |
virtual task body ();
|
virtual task body ();
|
start_item(trans);
|
start_item(trans);
|
trans.randomize() with {
|
trans.randomize() with {
|
_mode == binary;
|
_mode == binary;
|
_command == read;
|
_command == read;
|
address == 4'hffff;
|
address == 16'hFFFF;
|
(length_data > 1) -> (_reqinc == yes);
|
(length_data > 1) -> (_reqinc == yes);
|
_arbit == accept;
|
_arbit == accept;
|
} ;
|
} ;
|
finish_item(trans);
|
finish_item(trans);
|
endtask:body
|
endtask:body
|
| Line 1285... |
Line 1392... |
} ;
|
} ;
|
finish_item(trans);
|
finish_item(trans);
|
endtask:body
|
endtask:body
|
endclass:seq_6p10
|
endclass:seq_6p10
|
|
|
//-------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
//
|
//
|
// INTERNAL BUS
|
// INTERNAL BUS
|
//
|
//
|
//-------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
|
|
// 7.1 Apply UART read or write commands and give the UART the bus grant.
|
// 7.1 Apply UART read or write commands and give the UART the bus grant.
|
class seq_7p1 extends uart_base_sequence;
|
class seq_7p1 extends uart_base_sequence;
|
|
|
`uvm_object_utils(seq_7p1)
|
`uvm_object_utils(seq_7p1)
|
| Line 1334... |
Line 1441... |
_reqinc == yes;
|
_reqinc == yes;
|
} ;
|
} ;
|
finish_item(trans);
|
finish_item(trans);
|
endtask:body
|
endtask:body
|
endclass:seq_7p2
|
endclass:seq_7p2
|
No newline at end of file
|
No newline at end of file
|
|
|
|
//-------------------------------------------------------------------------------------------------
|
|
//
|
|
// INVALID COMMANDS
|
|
//
|
|
//-------------------------------------------------------------------------------------------------
|
|
|
|
// 8.1 Apply Invalid UART command in form of write binary command.
|
|
class seq_8p1 extends uart_base_sequence;
|
|
|
|
`uvm_object_utils(seq_8p1)
|
|
|
|
function new (string name="seq_8p1");
|
|
super.new(name);
|
|
endfunction:new
|
|
|
|
virtual task body ();
|
|
start_item(trans);
|
|
trans.randomize() with {
|
|
_mode == binary;
|
|
_command == invalid_write;
|
|
(length_data > 1) -> (_reqinc == yes);
|
|
_arbit == accept;
|
|
_reqinc == yes;
|
|
} ;
|
|
finish_item(trans);
|
|
endtask:body
|
|
endclass:seq_8p1
|
|
|
|
// 8.2 Apply Invalid UART command in form of read binary command.
|
|
class seq_8p2 extends uart_base_sequence;
|
|
|
|
`uvm_object_utils(seq_8p2)
|
|
|
|
function new (string name="seq_8p2");
|
|
super.new(name);
|
|
endfunction:new
|
|
|
|
virtual task body ();
|
|
start_item(trans);
|
|
trans.randomize() with {
|
|
_mode == binary;
|
|
_command == invalid_read;
|
|
(length_data > 1) -> (_reqinc == yes);
|
|
_arbit == declain;
|
|
_reqinc == yes;
|
|
} ;
|
|
finish_item(trans);
|
|
endtask:body
|
|
endclass:seq_8p2
|
