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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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//
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// UART2BUS VERIFICATION
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// UART2BUS VERIFICATION
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//
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//
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//-----------------------------------------------------------------------------
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//
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//-------------------------------------------------------------------------------------------------
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// CREATOR : HANY SALAH
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : INTERFACE
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// UNIT : INTERFACE
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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// TITLE : UART Interface
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// TITLE : REGISTER FILE BFM
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// DESCRIPTION: This
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// DESCRIPTION: THIS BUS FUNCTIONAL MODEL (BFM) ACTS AS ACTUAL REGISTER FILE CONNECTED TO THE DUT
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//-----------------------------------------------------------------------------
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// ACROSS THE NON-STANDARD INTERFACE. IT IS IMPLEMENTED IN THE MANNER THAT APPLY THE
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// COMMUNICATION PROTOCOL DESCRIPED IN THE DUT MICROARCHITECTURE SPECIFICATIONS
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//-------------------------------------------------------------------------------------------------
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// LOG DETAILS
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// LOG DETAILS
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//-------------
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 25122015 FILE CREATION
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// 1 HANY SALAH 25122015 FILE CREATION
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//-----------------------------------------------------------------------------
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// 2 HANY SALAH 20012016 ADD READ BLOCK ROUTINE
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
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// 3 HANY SALAH 11022016 IMPROVE BLOCK DESCRIPTION & ADD BLOCK COMMENTS
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// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
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//-------------------------------------------------------------------------------------------------
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// CREATOR'S PERMISSION
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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//-----------------------------------------------------------------------------
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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`include "defin_lib.svh"
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`include "defin_lib.svh"
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interface rf_interface (input bit clock, // Global Clock Signal
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interface rf_interface (input bit clock, // Global Clock Signal
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input bit reset); // Global Asynchronous Reset Signal
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input bit reset); // Global Asynchronous Reset Signal
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// Register File Side Signals
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// Register File Side Signals
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//
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//
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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logic [15:0] int_address; // Address Bus To Register File
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logic [15:0] int_address; // Address Bus To Register File
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logic [7:0] int_wr_data; // Write Data To Register File
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logic [7:0] int_wr_data; // Write Data To Register File
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logic int_write; // Write Contorl To Register File
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logic int_write; // Write Contorl To Register File
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logic [7:0] int_rd_data; // Read Data From Register File
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logic [7:0] int_rd_data; // Read Data From Register File
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logic int_read; // Read Control To Register File
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logic int_read; // Read Control To Register File
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// CONTROL SIGNALS
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// CONTROL SIGNALS
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//
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//
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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// This output is set when the testbench gives the bus access to the UART DUT
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logic int_gnt;
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logic int_gnt;
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// This input is activated whenever the UART DUT request to grant the bus access
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logic int_req;
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logic int_req;
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// Internal Variables
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// Internal Variables
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//
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//
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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// Memory of 64K bytes as Register File
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// Memory of 64K bytes as Register File
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byte register_file [`mem_size-1:0];
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byte register_file [`mem_size-1:0];
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// Operation Blocks
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// Operation Blocks
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//
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//
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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// This is the main operation always block that responds to the asynchronous reset. Every clock
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// positive edge, it check for both int_read & int_write inputs. if the int_write is activated,
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// it store the data forced on the int_wr_data into the memory location defined by the address
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// applied on the int_address port. if the int_read is activated, it load the data stored in the
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// memory location defined by the address applied on the int_address port.
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// It's forbidden to assert both the int_write & int_read signal in the same time.
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always
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always
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begin
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begin
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@(posedge clock or posedge reset);
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@(posedge clock or posedge reset);
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begin
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begin
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if (reset)
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if (reset)
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int_rd_data = read_mem_data(int_address);
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int_rd_data = read_mem_data(int_address);
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end
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end
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end
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end
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end
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end
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// Non Standard Routines
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// Non Standard Routines
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//
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//
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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// fill_byte routine is a function that fill only single byte in the register
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// fill_byte routine is a function that fill only a single byte in the register file defined by
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// file
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// the input address with the single byte identified by data.
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function void fill_byte (bit [`size-1:0] address,
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function void fill_byte (bit [`size-1:0] address,
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byte data);
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byte data);
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register_file[address] = data;
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register_file[address] = data;
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endfunction:fill_byte
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endfunction:fill_byte
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// fill_block routine is a function that fill continuous block of locations
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// fill_block routine is a function that fill continuous block of locations in the register file.
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// in the register file
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// The starting address identified by the address input and the data is defined by the dynamic
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// array data with length equal to block_length input.
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// In case that the block of memory locations includes the top memory location which meant that
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// the memory pointer(address) will reach its highest possible value and roll to zero. The imp-
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// lemented function has put this point in the concern
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function automatic void fill_block(bit [`size-1:0] address,
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function automatic void fill_block(bit [`size-1:0] address,
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ref byte data [],
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ref byte data [],
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int unsigned block_length);
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int unsigned block_length);
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for (int unsigned index = 0; index < block_length; index++)
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for (int unsigned index = 0; index < block_length; index++)
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begin
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begin
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// in case that the memory pointer has rolled over. the new address will be calculated from
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// the following relationship
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// The new address = the actual address - the whole memory size.
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if(address+index > `mem_size-1)
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begin
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register_file[address+index-`mem_size] = data [index];
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end
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else
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begin
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register_file[address+index] = data [index];
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register_file[address+index] = data [index];
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end
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end
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end
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endfunction:fill_block
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endfunction:fill_block
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// reset_mem routine is a function that fill reset the register file to contents
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// reset_mem routine is a function that fill reset the register file contents to zero
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// zero
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function void reset_mem();
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function void reset_mem();
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for (int unsigned index = 0; index < `mem_size; index++)
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for (int unsigned index = 0; index < `mem_size; index++)
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begin
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begin
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register_file[index] = 8'b0;
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register_file[index] = 8'b0;
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end
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end
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// read_mem_data routine is a function that load bus with the data content
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// read_mem_data routine is a function that load bus with the data content
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function byte read_mem_data(bit [`size-1:0] address);
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function byte read_mem_data(bit [`size-1:0] address);
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return register_file[address];
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return register_file[address];
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endfunction: read_mem_data
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endfunction: read_mem_data
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// This routine read adjacent block of memory location into dynamic array of data and the
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// starting address defined by the address input.
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// The point of memory pointer rolling over has been put in the consideration
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task automatic read_block(input int unsigned data_length,
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task automatic read_block(input int unsigned data_length,
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input bit [15:0] address,
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input bit [15:0] address,
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ref byte data []);
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ref byte data []);
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data = new [data_length];
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data = new [data_length];
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for (int unsigned index=0;index
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for (int unsigned index=0;index
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begin
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begin
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if (address+index > `mem_size-1)
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begin
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data[index] = read_mem_data(address+index-`mem_size);
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end
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else
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begin
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data[index] = read_mem_data(address+index);
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data[index] = read_mem_data(address+index);
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end
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end
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end
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endtask:read_block
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endtask:read_block
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//-----------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// MONITOR ROUTINES
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// MONITOR ROUTINES
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//
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//
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//-----------------------------------------
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//-------------------------------------------------------------------------------------------------
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// This routine capture both the data and the address of the current transaction across the non-
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// standard interface side.
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// When it is called, it is blocked till the raising edge of int_gnt input. And during the high
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// level of int_gnt input. This routine samples both int_read and int_write inputs every positive
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// edge of the clock signal. If int_read is active, it realizes that the current transaction is
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// read and sample the int_rd_data bus at the current clock tick.
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// If the int_write is active, it realizes that the current transaction is write and sample the
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// int_wr_data bus at the current clock tick.
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// Note : - The transaction address is the address of the first affected memory location.
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// - It's obvious that one of the signals int_read or int_write at least should be active
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// when the int_gnt is active. which is implemented through the error alarm below.
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task automatic capture_transaction (output bit[`size-1:0] address,
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task automatic capture_transaction (output bit[`size-1:0] address,
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ref byte data []);
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ref byte data [],
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int index;
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output int unsigned data_length);
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int unsigned index;
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index = 0;
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index = 0;
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@(posedge int_gnt);
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@(posedge int_gnt);
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while (int_gnt)
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while (int_gnt)
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begin
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begin
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@(posedge clock);
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@(posedge clock);
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begin
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begin
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data [index] = int_wr_data;
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data [index] = int_wr_data;
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end
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end
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else
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else
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begin
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begin
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$error("both int_write and int_read is inactive");
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$error("Both int_read and int_write is inactive while int_gnt is active");
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end
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end
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index++;
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index++;
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data_length = index;
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end
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end
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endtask:capture_transaction
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endtask:capture_transaction
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endinterface:rf_interface
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endinterface:rf_interface
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