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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// UART2BUS VERIFICATION
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// UART2BUS VERIFICATION
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//
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//
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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// CREATOR : HANY SALAH
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : INTERFACE
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// UNIT : INTERFACE
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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// TITLE : UART Arbiter
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// TITLE : UART Arbiter
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// DESCRIPTION: This
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// DESCRIPTION: THIS BFM ACT AS ARBITER CONNECTED TO THE DUT. ITS DUTY IS ONLY TO GIVE THE DUT THE
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//-----------------------------------------------------------------------------
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// BUS GRANT OR NOT.
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//-------------------------------------------------------------------------------------------------
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// LOG DETAILS
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// LOG DETAILS
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//-------------
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 29122015 FILE CREATION
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// 1 HANY SALAH 29122015 FILE CREATION
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//-----------------------------------------------------------------------------
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// 2 HANY SALAH 12022016 ENHANCE BLOCK DESCRIPTION & ADD COMMENTS
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
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//-------------------------------------------------------------------------------------------------
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// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// CREATOR'S PERMISSION
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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//-----------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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interface uart_arbiter (input bit clock,
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interface uart_arbiter (input bit clock,
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input bit reset);
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input bit reset);
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// Bus Control Signals
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// Bus Control Signals
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//
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//
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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logic int_req; // Request Internal Bus Access
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logic int_req; // Request Internal Bus Access
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logic int_gnt; // Grant Internal Bus Access
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logic int_gnt; // Grant Internal Bus Access
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// Arbiter Control Signals
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// Arbiter Control Signals
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//
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//
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//--------------------------------
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//-------------------------------------------------------------------------------------------------
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// When this routine is called, it wait the request signal activation to give the bus grant to
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// the DUT.
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task accept_req ();
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task accept_req ();
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wait (int_req);
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wait (int_req);
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int_gnt = 1'b1;
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int_gnt = 1'b1;
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endtask:accept_req
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endtask:accept_req
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// When this routine is called, it wait the request signal activation and then declain the
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// the request buy set int_gnt to zero.
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task declain_req ();
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task declain_req ();
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wait (int_req);
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wait (int_req);
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int_gnt = 1'b0;
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int_gnt = 1'b0;
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endtask:declain_req
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endtask:declain_req
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