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[/] [uart2bus_testbench/] [trunk/] [tb/] [test/] [uart_test.svh] - Diff between revs 17 and 18

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Rev 17 Rev 18
Line 19... Line 19...
// VERSION      NAME        DATE        DESCRIPTION
// VERSION      NAME        DATE        DESCRIPTION
//    1       HANY SALAH    10012016    FILE CREATION
//    1       HANY SALAH    10012016    FILE CREATION
//    2       HANY SALAH    20012016    ADD BINARY MODE TESTS AND INVALID TESTS
//    2       HANY SALAH    20012016    ADD BINARY MODE TESTS AND INVALID TESTS
//    3       HANY SALAH    12022016    IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
//    3       HANY SALAH    12022016    IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
//    4       HANY SALAH    26062017    ADD COVERAGE DRIVEN TEST
//    4       HANY SALAH    26062017    ADD COVERAGE DRIVEN TEST
 
//    5       HANY SALAH    22072017    ADD THE DASHBOARD SETTINGS
//-------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
//-------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------
 
 
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  `endif
  `endif
  int               hit_text_cov=90;
  int               hit_text_cov=90;
  int               hit_bin_cov=90;
  int               hit_bin_cov=90;
  int               hit_mode_cov=90;
  int               hit_mode_cov=90;
 
 
 
   uart_dashboard       dashboard;
 
 
 
 
  `uvm_component_utils_begin(uart_base_test)
  `uvm_component_utils_begin(uart_base_test)
     `uvm_field_int(matched,UVM_ALL_ON)
     `uvm_field_int(matched,UVM_ALL_ON)
  `uvm_component_utils_end
  `uvm_component_utils_end
 
 
  function new (string name,uvm_component parent);
  function new (string name,uvm_component parent);
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    `else
    `else
     report_server = new();
     report_server = new();
    `endif
    `endif
    env_configuration();
    env_configuration();
    TE_configuration();
    TE_configuration();
 
     dashboard = uart_dashboard::type_id::create("uart_dashboard");
 
     uvm_resource_db#(uart_dashboard)::set("shared_cloud","dashboard",dashboard,null);
    uvm_config_db#(uart_config)::set(this,"*","UART_CONFIGURATION",_config);
    uvm_config_db#(uart_config)::set(this,"*","UART_CONFIGURATION",_config);
    uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
 
    uvm_resource_db #(int)::set("coverage_cloud","binary_coverage",0,null);
 
    uvm_resource_db #(int)::set("coverage_cloud","general_coverage",0,null);
 
  endfunction:build_phase
  endfunction:build_phase
 
 
  function void connect_phase (uvm_phase phase);
  function void connect_phase (uvm_phase phase);
    super.connect_phase(phase);
    super.connect_phase(phase);
  endfunction:connect_phase
  endfunction:connect_phase
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    uvm_resource_db#(int)::set("Reporting","matched_packets",0,null);
    uvm_resource_db#(int)::set("Reporting","matched_packets",0,null);
    uvm_root::get().set_timeout(10s);
    uvm_root::get().set_timeout(10s);
    //uvm_root::get().finish_on_completion=1'b0;
    //uvm_root::get().finish_on_completion=1'b0;
 endfunction // TE_configuration
 endfunction // TE_configuration
 
 
 
   function void end_of_elaboration_phase (uvm_phase phase);
 
      super.end_of_elaboration_phase(phase);
 
      //dashboard.set_cov_threshold(80,80,80,80,80);
 
   endfunction // end_of_elaboration_phase
 
 
  task run_phase (uvm_phase phase);
  task run_phase (uvm_phase phase);
    phase.phase_done.set_drain_time(this,5000);
    phase.phase_done.set_drain_time(this,5000);
  endtask:run_phase
  endtask:run_phase
 
 
  function void report_phase (uvm_phase phase);
  function void report_phase (uvm_phase phase);
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      seq23 = seq_2p10::type_id::create("seq23");
      seq23 = seq_2p10::type_id::create("seq23");
      seq24 = seq_2p11::type_id::create("seq24");
      seq24 = seq_2p11::type_id::create("seq24");
      seq25 = seq_2p12::type_id::create("seq25");
      seq25 = seq_2p12::type_id::create("seq25");
      seq26 = seq_2p13::type_id::create("seq26");
      seq26 = seq_2p13::type_id::create("seq26");
      uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
      uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
      //uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
 
    endfunction:build_phase
    endfunction:build_phase
 
 
    task run_phase (uvm_phase phase);
    task run_phase (uvm_phase phase);
      super.run_phase(phase);
      super.run_phase(phase);
      phase.raise_objection(this);
      phase.raise_objection(this);
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//
//
//                        Coverage Driven Test
//                        Coverage Driven Test
//
//
//-------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------
 
 
class cover_driven_test extends uart_base_test;
class coverage_base_test extends uart_base_test;
 
 
   rand int unsigned testnumber;
   rand int unsigned testnumber;
 
 
   bit     coverage_hit=1'b0;
   bit     coverage_hit=1'b0;
 
 
   int     iteration=0;
   int     iteration=0;
 
 
   parameter MAX_ITER=500;
   parameter MAX_ITER=10000;
 
 
 
   uvm_table_printer cov_pr;
 
 
   // Text write tests
   // Text write tests
    seq_1p1   seq1;
    seq_1p1   seq1;
    seq_1p2   seq2;
    seq_1p2   seq2;
    seq_1p3   seq3;
    seq_1p3   seq3;
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   // GRANT test
   // GRANT test
   seq_7p1    seq44;
   seq_7p1    seq44;
   seq_7p2    seq45;
   seq_7p2    seq45;
 
 
 
 
   `uvm_component_utils(cover_driven_test)
   `uvm_component_utils(coverage_base_test)
 
 
   constraint validtest{testnumber inside{[0:45]};
   constraint validtest{testnumber inside{[0:45]};
                        testnumber != 13;
                        testnumber != 13;
                        testnumber != 9;
                        testnumber != 9;
                        testnumber != 19;
                        testnumber != 19;
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      seq41     = seq_6p8::type_id::create("seq41");
      seq41     = seq_6p8::type_id::create("seq41");
      seq42     = seq_6p9::type_id::create("seq42");
      seq42     = seq_6p9::type_id::create("seq42");
      seq43     = seq_6p10::type_id::create("seq43");
      seq43     = seq_6p10::type_id::create("seq43");
      seq44     = seq_7p1::type_id::create("seq44");
      seq44     = seq_7p1::type_id::create("seq44");
      seq45     = seq_7p2::type_id::create("seq45");
      seq45     = seq_7p2::type_id::create("seq45");
 
      cov_pr    = new();
   endfunction // build_phase
   endfunction // build_phase
 
 
 
   function void end_of_elaboration_phase (uvm_phase phase);
 
      super.end_of_elaboration_phase(phase);
 
      cov_pr.knobs.default_radix=UVM_DEC;
 
   endfunction // end_of_elaboration_phase
 
 
   task run_phase (uvm_phase phase);
   task run_phase (uvm_phase phase);
      super.run_phase(phase);
      super.run_phase(phase);
      phase.raise_objection(this);
      phase.raise_objection(this);
      while(coverage_hit==1'b0 && (iteration < MAX_ITER)) begin
      while(!dashboard.hit_coverage && (iteration < MAX_ITER)) begin
     // while(iteration < 1000) begin
     // while(iteration < 1000) begin
         iteration++;
         iteration++;
         randomize();
         randomize();
         case(testnumber)
         case(testnumber)
           0:
           0:
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           default:
           default:
             begin
             begin
                `uvm_error("TE","Invalid_test")
                `uvm_error("TE","Invalid_test")
             end
             end
         endcase // case (testnumber)
         endcase // case (testnumber)
         evaluate_coverage();
      end // while (!dashboard.hit_coverage && (iteration < MAX_ITER))
      end // while (coverage_hit==1'b0)
 
      phase.drop_objection(this);
      phase.drop_objection(this);
   endtask // run_phase
   endtask // run_phase
 
 
   function void evaluate_coverage();
 
       int text_cov;
 
       int bin_cov;
 
       int mode_cov;
 
       uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_cov);
 
      uvm_resource_db#(int)::read_by_name("coverage_cloud","general_coverage",mode_cov);
 
      uvm_resource_db#(int)::read_by_name("coverage_cloud","binary_coverage",bin_cov);
 
       if((text_cov >= hit_text_cov) &&
 
          (bin_cov  >= hit_bin_cov) &&
 
          (mode_cov >= hit_mode_cov)) coverage_hit=1'b1;
 
   endfunction // evaluate_coverage
 
 
 
   function void report_phase(uvm_phase phase);
   function void report_phase(uvm_phase phase);
      int  text_cov;
      int  text_cov;
      int  mode_cov;
      int  mode_cov;
      int  bin_cov;
      int  bin_cov;
      super.report_phase(phase);
      super.report_phase(phase);
     if(!(iteration
     if(!dashboard.hit_coverage)
       begin
       begin
          uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_cov);
          `uvm_warning("SIM","Coverage not hit");
          uvm_resource_db#(int)::read_by_name("coverage_cloud","binary_coverage",bin_cov);
          dashboard.print(cov_pr);
          uvm_resource_db#(int)::read_by_name("coverage_cloud","general_coverage",mode_cov);
 
        `uvm_warning("SIM",$sformatf("coverage not hit and reached \n textcov:%0d\nmodecov:%0d\nbincov:%0d",text_cov,mode_cov,bin_cov));
 
       end
       end
     else begin
     else begin
        `uvm_info("SIM",$sformatf("Simulation hit the coverage successfully by %0d transactions",iteration),UVM_NONE);
        `uvm_info("SIM",$sformatf("Simulation hit the coverage successfully by %0d transactions",iteration),UVM_NONE);
 
        dashboard.print(cov_pr);
     end
     end
   endfunction // report_phase
   endfunction // report_phase
 
 
endclass // cover_driven_test
endclass // coverage_base_test
endclass // coverage_base_test
endclass // coverage_base_test

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