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https://opencores.org/ocsvn/uart6551/uart6551/trunk
[/] [uart6551/] [trunk/] [trunk/] [rtl/] [pci32_config.sv] - Diff between revs 11 and 12
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Rev 11 |
Rev 12 |
Line 118... |
Line 118... |
reg [31:0] cfg_dat [0:63];
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reg [31:0] cfg_dat [0:63];
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reg [31:0] cfg_out;
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reg [31:0] cfg_out;
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reg [7:0] irq_line;
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reg [7:0] irq_line;
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initial begin
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initial begin
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for (n1 = 0; n1 < 32; n1 = n1 + 1)
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for (n1 = 0; n1 < 64; n1 = n1 + 1)
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cfg_dat[n1] = 'd0;
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cfg_dat[n1] = 'd0;
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end
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end
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wire cs = cs_config_i &&
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wire cs = cs_config_i &&
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adr_i[27:20]==CFG_BUS &&
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adr_i[27:20]==CFG_BUS &&
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Line 194... |
Line 194... |
if (sel_i[0]) irq_line <= dat_i[7:0];
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if (sel_i[0]) irq_line <= dat_i[7:0];
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default:
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default:
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cfg_dat[adr_i[7:2]] <= dat_i;
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cfg_dat[adr_i[7:2]] <= dat_i;
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endcase
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endcase
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else
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else
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case(adr_i[7:3])
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case(adr_i[7:2])
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5'h00: cfg_out <= {CFG_DEVICE_ID,CFG_VENDOR_ID};
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5'h00: cfg_out <= {CFG_DEVICE_ID,CFG_VENDOR_ID};
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5'h01: cfg_out <= {stato_reg,cmdo_reg};
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5'h01: cfg_out <= {stato_reg,cmdo_reg};
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5'h02: cfg_out <= {
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5'h02: cfg_out <= {
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CFG_CLASS,CFG_SUBCLASS,CFG_PROGIF,CFG_REVISION_ID};
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CFG_CLASS,CFG_SUBCLASS,CFG_PROGIF,CFG_REVISION_ID};
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5'h03: cfg_out <= {8'h00,
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5'h03: cfg_out <= {8'h00,
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