| Line 108... |
Line 108... |
wire lineStatusChange;
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wire lineStatusChange;
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reg rxToutIe; // receiver timeout interrupt enable
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reg rxToutIe; // receiver timeout interrupt enable
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reg [3:0] rxThres; // receiver threshold for interrupt
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reg [3:0] rxThres; // receiver threshold for interrupt
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reg [3:0] txThres; // transmitter threshold for interrupt
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reg [3:0] txThres; // transmitter threshold for interrupt
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reg rxTout; // receiver timeout
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reg rxTout; // receiver timeout
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wire [11:0] rxCnt; // reciever counter value
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wire [9:0] rxCnt; // reciever counter value
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reg [7:0] rxToutMax;
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reg [7:0] rxToutMax;
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reg [2:0] irqenc; // encoded irq cause
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reg [2:0] irqenc; // encoded irq cause
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wire rxITrig; // receiver interrupt trigger level
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wire rxITrig; // receiver interrupt trigger level
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wire txITrig; // transmitter interrupt trigger level
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wire txITrig; // transmitter interrupt trigger level
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// reciever errors
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// reciever errors
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| Line 145... |
Line 145... |
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assign rxITrig = rxQued >= rxThres;
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assign rxITrig = rxQued >= rxThres;
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assign txITrig = txQued <= txThres;
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assign txITrig = txQued <= txThres;
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wire rxDRQ1 = (fifoEnable ? rxITrig : ~rxEmpty);
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wire rxDRQ1 = (fifoEnable ? rxITrig : ~rxEmpty);
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wire txDRQ1 = (fifoEnable ? txITrig : txEmpty);
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wire txDRQ1 = (fifoEnable ? txITrig : txEmpty);
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assign rxDRQ = dmaEnable & rxDRQ1;
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assign rxDRQ_o = dmaEnable & rxDRQ1;
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assign txDRQ = dmaEnable & txDRQ1;
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assign txDRQ_o = dmaEnable & txDRQ1;
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wire rxIRQ = rxIe & rxDRQ1;
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wire rxIRQ = rxIe & rxDRQ1;
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wire txIRQ = txIe & txDRQ1;
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wire txIRQ = txIe & txDRQ1;
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reg [7:0] cmd0, cmd1, cmd2, cmd3;
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reg [7:0] cmd0, cmd1, cmd2, cmd3;
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reg [7:0] ctrl0, ctrl1, ctrl2, ctrl3;
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reg [7:0] ctrl0, ctrl1, ctrl2, ctrl3;
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| Line 581... |
Line 581... |
// frame size is one less
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// frame size is one less
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assign frameSize = {wordLength + 4'd1 + stopBits[2:1] + parityCtrl[0], stopBits[0],3'b0} - 1;
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assign frameSize = {wordLength + 4'd1 + stopBits[2:1] + parityCtrl[0], stopBits[0],3'b0} - 1;
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//-----------------------------------------------------
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//-----------------------------------------------------
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// encode IRQ mailbox
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// encode IRQ mailbox
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always @(rxDRQ or rxTout or txDRQ or lineStatusChange or modemStatusChange)
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always @(rxDRQ_o or rxTout or txDRQ_o or lineStatusChange or modemStatusChange)
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irqenc <=
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irqenc <=
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lineStatusChange ? 3'd0 :
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lineStatusChange ? 3'd0 :
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~rxDRQ ? 3'd1 :
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~rxDRQ_o ? 3'd1 :
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rxTout ? 3'd2 :
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rxTout ? 3'd2 :
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~txDRQ ? 3'd3 :
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~txDRQ_o ? 3'd3 :
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modemStatusChange ? 3'd4 :
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modemStatusChange ? 3'd4 :
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3'd0;
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3'd0;
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endmodule
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endmodule
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