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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// BSD 3-Clause License
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// it under the terms of the GNU Lesser General Public License as published
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// Redistribution and use in source and binary forms, with or without
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// by the Free Software Foundation, either version 3 of the License, or
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// modification, are permitted provided that the following conditions are met:
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// 1. Redistributions of source code must retain the above copyright notice, this
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// list of conditions and the following disclaimer.
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// along with this program. If not, see .
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`define UART_TRB 2'd0 // transmit/receive buffer
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`define UART_TRB 2'd0 // transmit/receive buffer
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`define UART_STAT 2'd1
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`define UART_STAT 2'd1
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cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,
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cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,
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rxd_i, txd_o, data_present,
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rxd_i, txd_o, data_present,
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rxDRQ_o, txDRQ_o,
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rxDRQ_o, txDRQ_o,
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xclk_i, RxC_i
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xclk_i, RxC_i
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);
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);
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parameter pClkFreq = 40;
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parameter pCounterBits = 24;
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parameter pCounterBits = 24;
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parameter pFifoSize = 1024;
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parameter pFifoSize = 1024;
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parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock
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parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock
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parameter HIGH = 1'b1;
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parameter HIGH = 1'b1;
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parameter LOW = 1'b0;
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parameter LOW = 1'b0;
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reg deltaRi;
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reg deltaRi;
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// fifo
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// fifo
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reg rxFifoClear;
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reg rxFifoClear;
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reg txFifoClear;
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reg txFifoClear;
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reg txClear;
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reg fifoEnable;
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reg fifoEnable;
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wire [3:0] rxQued;
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wire [3:0] rxQued;
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wire [3:0] txQued;
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wire [3:0] txQued;
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// test
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// test
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.REGISTER_OUTPUT(1)
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.REGISTER_OUTPUT(1)
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) uag1
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) uag1
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.ce_i(1'b1),
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.ce_i(1'b1),
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.i(cs),
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.rid_i('d0),
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.wid_i('d0),
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.i(cs & ~we_i),
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.we_i(cs & we_i),
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.we_i(cs & we_i),
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.o(ack_o)
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.o(ack_o),
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.rid_o(),
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.wid_o()
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);
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);
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uart6551Rx uart_rx0
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uart6551Rx uart_rx0
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(
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(
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.rst(rst_i),
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.rst(rst_i),
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.frameSize(frameSize), // 16 x 10 bits
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.frameSize(frameSize), // 16 x 10 bits
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.wordLength(wordLength),// 8 bits
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.wordLength(wordLength),// 8 bits
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.parityCtrl(parityCtrl),// no parity
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.parityCtrl(parityCtrl),// no parity
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.baud16x_ce(baud16),
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.baud16x_ce(baud16),
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.cts(ctsx[1]|~hwfc),
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.cts(ctsx[1]|~hwfc),
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.clear(clear),
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.clear(txClear),
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.txd(txd1),
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.txd(txd1),
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.full(txFull),
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.full(txFull),
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.empty(txEmpty),
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.empty(txEmpty),
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.qcnt(txQued)
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.qcnt(txQued)
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);
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);
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txBreak <= 1'b0;
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txBreak <= 1'b0;
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// Fifo control
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// Fifo control
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txFifoClear <= 1'b1;
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txFifoClear <= 1'b1;
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rxFifoClear <= 1'b1;
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rxFifoClear <= 1'b1;
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txClear <= 1'b1;
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fifoEnable <= 1'b1;
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fifoEnable <= 1'b1;
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// Test
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// Test
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llb <= 1'b0;
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llb <= 1'b0;
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selCD <= 1'b0;
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selCD <= 1'b0;
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accessCD <= 1'b0;
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accessCD <= 1'b0;
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else begin
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else begin
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//llb <= 1'b1;
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//llb <= 1'b1;
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rxFifoClear <= 1'b0;
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rxFifoClear <= 1'b0;
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txFifoClear <= 1'b0;
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txFifoClear <= 1'b0;
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txClear <= 1'b0;
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ctrl2[1] <= 1'b0;
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ctrl2[1] <= 1'b0;
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ctrl2[2] <= 1'b0;
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ctrl2[2] <= 1'b0;
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if (ack_o & we) begin
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if (ack_o & we) begin
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case (adr_h) // synopsys full_case parallel_case
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case (adr_h) // synopsys full_case parallel_case
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if (sel[3]) begin
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if (sel[3]) begin
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ctrl3 <= dati[31:24];
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ctrl3 <= dati[31:24];
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hwfc <= dati[24];
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hwfc <= dati[24];
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dmaEnable <= dati[26];
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dmaEnable <= dati[26];
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baudRateSel[4] <= dati[27];
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baudRateSel[4] <= dati[27];
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txClear <= dati[29];
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selCD <= dati[30];
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selCD <= dati[30];
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accessCD <= dati[31];
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accessCD <= dati[31];
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end
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end
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end
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end
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always @(posedge clk_i)
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always @(posedge clk_i)
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xClkSrc <= baudRateSel==5'd0;
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xClkSrc <= baudRateSel==5'd0;
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wire [pCounterBits-1:0] bclkdiv;
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wire [pCounterBits-1:0] bclkdiv;
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uart6551BaudLUT #(pCounterBits) ublt1 (.a(baudRateSel), .o(bclkdiv));
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uart6551BaudLUT #(.pClkFreq(pClkFreq), .pCounterBits(pCounterBits)) ublt1 (.a(baudRateSel), .o(bclkdiv));
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reg [pCounterBits-1:0] clkdiv2;
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reg [pCounterBits-1:0] clkdiv2;
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always @(posedge clk_i)
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always @(posedge clk_i)
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clkdiv2 <= selCD ? clkdiv : bclkdiv;
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clkdiv2 <= selCD ? clkdiv : bclkdiv;
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