| Line 1... |
Line 1... |
// ============================================================================
|
// ============================================================================
|
// __
|
// __
|
// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo
|
// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo
|
// \ __ / All rights reserved.
|
// \ __ / All rights reserved.
|
// \/_// robfinch@finitron.ca
|
// \/_// robfinch@finitron.ca
|
// ||
|
// ||
|
//
|
//
|
//
|
//
|
// This source file is free software: you can redistribute it and/or modify
|
// BSD 3-Clause License
|
// it under the terms of the GNU Lesser General Public License as published
|
// Redistribution and use in source and binary forms, with or without
|
// by the Free Software Foundation, either version 3 of the License, or
|
// modification, are permitted provided that the following conditions are met:
|
// (at your option) any later version.
|
|
//
|
//
|
// This source file is distributed in the hope that it will be useful,
|
// 1. Redistributions of source code must retain the above copyright notice, this
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// list of conditions and the following disclaimer.
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
// GNU General Public License for more details.
|
|
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
// along with this program. If not, see .
|
// this list of conditions and the following disclaimer in the documentation
|
|
// and/or other materials provided with the distribution.
|
|
//
|
|
// 3. Neither the name of the copyright holder nor the names of its
|
|
// contributors may be used to endorse or promote products derived from
|
|
// this software without specific prior written permission.
|
|
//
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
`define UART_TRB 2'd0 // transmit/receive buffer
|
`define UART_TRB 2'd0 // transmit/receive buffer
|
`define UART_STAT 2'd1
|
`define UART_STAT 2'd1
|
| Line 31... |
Line 44... |
cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,
|
cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,
|
rxd_i, txd_o, data_present,
|
rxd_i, txd_o, data_present,
|
rxDRQ_o, txDRQ_o,
|
rxDRQ_o, txDRQ_o,
|
xclk_i, RxC_i
|
xclk_i, RxC_i
|
);
|
);
|
|
parameter pClkFreq = 40;
|
parameter pCounterBits = 24;
|
parameter pCounterBits = 24;
|
parameter pFifoSize = 1024;
|
parameter pFifoSize = 1024;
|
parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock
|
parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock
|
parameter HIGH = 1'b1;
|
parameter HIGH = 1'b1;
|
parameter LOW = 1'b0;
|
parameter LOW = 1'b0;
|
| Line 132... |
Line 146... |
reg deltaRi;
|
reg deltaRi;
|
|
|
// fifo
|
// fifo
|
reg rxFifoClear;
|
reg rxFifoClear;
|
reg txFifoClear;
|
reg txFifoClear;
|
|
reg txClear;
|
reg fifoEnable;
|
reg fifoEnable;
|
wire [3:0] rxQued;
|
wire [3:0] rxQued;
|
wire [3:0] txQued;
|
wire [3:0] txQued;
|
|
|
// test
|
// test
|
| Line 191... |
Line 206... |
.REGISTER_OUTPUT(1)
|
.REGISTER_OUTPUT(1)
|
) uag1
|
) uag1
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.ce_i(1'b1),
|
.ce_i(1'b1),
|
.i(cs),
|
.rid_i('d0),
|
|
.wid_i('d0),
|
|
.i(cs & ~we_i),
|
.we_i(cs & we_i),
|
.we_i(cs & we_i),
|
.o(ack_o)
|
.o(ack_o),
|
|
.rid_o(),
|
|
.wid_o()
|
);
|
);
|
|
|
uart6551Rx uart_rx0
|
uart6551Rx uart_rx0
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
| Line 243... |
Line 262... |
.frameSize(frameSize), // 16 x 10 bits
|
.frameSize(frameSize), // 16 x 10 bits
|
.wordLength(wordLength),// 8 bits
|
.wordLength(wordLength),// 8 bits
|
.parityCtrl(parityCtrl),// no parity
|
.parityCtrl(parityCtrl),// no parity
|
.baud16x_ce(baud16),
|
.baud16x_ce(baud16),
|
.cts(ctsx[1]|~hwfc),
|
.cts(ctsx[1]|~hwfc),
|
.clear(clear),
|
.clear(txClear),
|
.txd(txd1),
|
.txd(txd1),
|
.full(txFull),
|
.full(txFull),
|
.empty(txEmpty),
|
.empty(txEmpty),
|
.qcnt(txQued)
|
.qcnt(txQued)
|
);
|
);
|
| Line 296... |
Line 315... |
|
|
txBreak <= 1'b0;
|
txBreak <= 1'b0;
|
// Fifo control
|
// Fifo control
|
txFifoClear <= 1'b1;
|
txFifoClear <= 1'b1;
|
rxFifoClear <= 1'b1;
|
rxFifoClear <= 1'b1;
|
|
txClear <= 1'b1;
|
fifoEnable <= 1'b1;
|
fifoEnable <= 1'b1;
|
// Test
|
// Test
|
llb <= 1'b0;
|
llb <= 1'b0;
|
selCD <= 1'b0;
|
selCD <= 1'b0;
|
accessCD <= 1'b0;
|
accessCD <= 1'b0;
|
| Line 307... |
Line 327... |
else begin
|
else begin
|
|
|
//llb <= 1'b1;
|
//llb <= 1'b1;
|
rxFifoClear <= 1'b0;
|
rxFifoClear <= 1'b0;
|
txFifoClear <= 1'b0;
|
txFifoClear <= 1'b0;
|
|
txClear <= 1'b0;
|
ctrl2[1] <= 1'b0;
|
ctrl2[1] <= 1'b0;
|
ctrl2[2] <= 1'b0;
|
ctrl2[2] <= 1'b0;
|
|
|
if (ack_o & we) begin
|
if (ack_o & we) begin
|
case (adr_h) // synopsys full_case parallel_case
|
case (adr_h) // synopsys full_case parallel_case
|
| Line 399... |
Line 420... |
if (sel[3]) begin
|
if (sel[3]) begin
|
ctrl3 <= dati[31:24];
|
ctrl3 <= dati[31:24];
|
hwfc <= dati[24];
|
hwfc <= dati[24];
|
dmaEnable <= dati[26];
|
dmaEnable <= dati[26];
|
baudRateSel[4] <= dati[27];
|
baudRateSel[4] <= dati[27];
|
|
txClear <= dati[29];
|
selCD <= dati[30];
|
selCD <= dati[30];
|
accessCD <= dati[31];
|
accessCD <= dati[31];
|
end
|
end
|
end
|
end
|
|
|
| Line 418... |
Line 440... |
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
xClkSrc <= baudRateSel==5'd0;
|
xClkSrc <= baudRateSel==5'd0;
|
|
|
wire [pCounterBits-1:0] bclkdiv;
|
wire [pCounterBits-1:0] bclkdiv;
|
uart6551BaudLUT #(pCounterBits) ublt1 (.a(baudRateSel), .o(bclkdiv));
|
uart6551BaudLUT #(.pClkFreq(pClkFreq), .pCounterBits(pCounterBits)) ublt1 (.a(baudRateSel), .o(bclkdiv));
|
|
|
reg [pCounterBits-1:0] clkdiv2;
|
reg [pCounterBits-1:0] clkdiv2;
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
clkdiv2 <= selCD ? clkdiv : bclkdiv;
|
clkdiv2 <= selCD ? clkdiv : bclkdiv;
|
|
|
