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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// BSD 3-Clause License
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// it under the terms of the GNU Lesser General Public License as published
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// Redistribution and use in source and binary forms, with or without
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// by the Free Software Foundation, either version 3 of the License, or
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// modification, are permitted provided that the following conditions are met:
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// (at your option) any later version.
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// This source file is distributed in the hope that it will be useful,
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// list of conditions and the following disclaimer.
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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//
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// GNU General Public License for more details.
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// this list of conditions and the following disclaimer in the documentation
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//
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// and/or other materials provided with the distribution.
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// You should have received a copy of the GNU General Public License
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//
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// along with this program. If not, see .
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module uart6551BaudLUT(a, o);
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module uart6551BaudLUT(a, o);
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parameter CLK_FREQ = 100;
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parameter pCounterBits = 24;
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parameter pCounterBits = 24;
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input [4:0] a;
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input [4:0] a;
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output reg [pCounterBits-1:0] o;
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output reg [pCounterBits-1:0] o;
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/*
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// table for a 50.000MHz reference clock
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// table for a 50.000MHz reference clock
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// value = 50,000,000 / (baud * 16)
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// value = 50,000,000 / (baud * 16)
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always @(a)
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always_comb
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case (a) // synopsys full_case parallel_case
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case (a) // synopsys full_case parallel_case
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5'd0: o <= 0;
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5'd0: o <= 0;
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5'd1: o <= 24'd62500; // 50 baud
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5'd1: o <= 24'd62500; // 50 baud
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5'd2: o <= 24'd41667; // 75 baud
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5'd2: o <= 24'd41667; // 75 baud
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5'd3: o <= 24'd28617; // 109.92 baud
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5'd3: o <= 24'd28617; // 109.92 baud
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5'd19: o <= 24'd14; // 230400 baud
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5'd19: o <= 24'd14; // 230400 baud
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5'd20: o <= 24'd7; // 460800 baud
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5'd20: o <= 24'd7; // 460800 baud
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5'd21: o <= 24'd3; // 921600 baud
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5'd21: o <= 24'd3; // 921600 baud
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default: o <= 24'd326; // 9600 baud
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default: o <= 24'd326; // 9600 baud
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endcase
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endcase
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*/
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// table for a 40.000MHz reference clock
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// value = 40,000,000 / (baud * 16)
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always_comb
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if (CLK_FREQ==40)
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case (a) // synopsys full_case parallel_case
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5'd0: o <= 0;
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5'd1: o <= 24'd50000; // 50 baud
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5'd2: o <= 24'd33333; // 75 baud
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5'd3: o <= 24'd22744; // 109.92 baud
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5'd4: o <= 24'd18576; // 134.58 baud
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5'd5: o <= 24'd16667; // 150 baud
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5'd6: o <= 24'd8333; // 300 baud
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5'd7: o <= 24'd4167; // 600 baud
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5'd8: o <= 24'd2083; // 1200 baud
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5'd9: o <= 24'd1389; // 1800 baud
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5'd10: o <= 24'd1042; // 2400 baud
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5'd11: o <= 24'd694; // 3600 baud
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5'd12: o <= 24'd521; // 4800 baud
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5'd13: o <= 24'd347; // 7200 baud
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5'd14: o <= 24'd260; // 9600 baud
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5'd15: o <= 24'd130; // 19200 baud
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5'd16: o <= 24'd65; // 38400 baud
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5'd17: o <= 24'd43; // 57600 baud
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5'd18: o <= 24'd22; // 115200 baud
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5'd19: o <= 24'd11; // 230400 baud
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5'd20: o <= 24'd5; // 460800 baud
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5'd21: o <= 24'd3; // 921600 baud
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default: o <= 24'd260; // 9600 baud
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endcase
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else if (CLK_FREQ==60)
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// table for a 60.000MHz reference clock
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case (a) // synopsys full_case parallel_case
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5'd0: o <= 0;
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5'd1: o <= 24'd75000; // 50 baud
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5'd2: o <= 24'd50000; // 75 baud
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5'd3: o <= 24'd34116; // 109.92 baud
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5'd4: o <= 24'd27864; // 134.58 baud
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5'd5: o <= 24'd25000; // 150 baud
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5'd6: o <= 24'd12500; // 300 baud
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5'd7: o <= 24'd6250; // 600 baud
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5'd8: o <= 24'd3125; // 1200 baud
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5'd9: o <= 24'd2083; // 1800 baud
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5'd10: o <= 24'd1563; // 2400 baud
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5'd11: o <= 24'd1042; // 3600 baud
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5'd12: o <= 24'd781; // 4800 baud
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5'd13: o <= 24'd521; // 7200 baud
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5'd14: o <= 24'd391; // 9600 baud
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5'd15: o <= 24'd195; // 19200 baud
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5'd16: o <= 24'd98; // 38400 baud
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5'd17: o <= 24'd65; // 57600 baud
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5'd18: o <= 24'd33; // 115200 baud
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5'd19: o <= 24'd16; // 230400 baud
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5'd20: o <= 24'd8; // 460800 baud
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5'd21: o <= 24'd4; // 921600 baud
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default: o <= 24'd391; // 9600 baud
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endcase
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else if (CLK_FREQ==100)
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// 100MHz
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case (a) // synopsys full_case parallel_case
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5'd0: o <= 0;
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5'd1: o <= 24'd125000; // 50 baud
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5'd2: o <= 24'd83333; // 75 baud
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5'd3: o <= 24'd56860; // 109.92 baud
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5'd4: o <= 24'd46441; // 134.58 baud
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5'd5: o <= 24'd41667; // 150 baud
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5'd6: o <= 24'd20833; // 300 baud
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5'd7: o <= 24'd10417; // 600 baud
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5'd8: o <= 24'd5208; // 1200 baud
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5'd9: o <= 24'd3472; // 1800 baud
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5'd10: o <= 24'd2604; // 2400 baud
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5'd11: o <= 24'd1736; // 3600 baud
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5'd12: o <= 24'd1302; // 4800 baud
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5'd13: o <= 24'd868; // 7200 baud
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5'd14: o <= 24'd651; // 9600 baud
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5'd15: o <= 24'd326; // 19200 baud
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5'd16: o <= 24'd163; // 38400 baud
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5'd17: o <= 24'd109; // 57600 baud
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5'd18: o <= 24'd54; // 115200 baud
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5'd19: o <= 24'd27; // 230400 baud
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5'd20: o <= 24'd14; // 460800 baud
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5'd21: o <= 24'd7; // 921600 baud
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default: o <= 24'd651; // 9600 baud
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endcase
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endmodule
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endmodule
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