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[/] [uart6551/] [trunk/] [trunk/] [rtl/] [uart6551Fifo.sv] - Diff between revs 2 and 4
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2003-2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2003-2021 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module uart6551Fifo(clk, rst, wr, rd, din, dout, ctr, full, empty);
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module uart6551Fifo(clk, rst, wr, rd, din, dout, ctr, full, empty);
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parameter WID=8;
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parameter WID=8;
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parameter DEP=16;
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parameter DEP=16;
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localparam pCtrBits = $clog2(DEP)-1;
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localparam pCtrBits = $clog2(DEP-1);
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input clk;
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input clk;
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input rst;
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input rst;
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input wr;
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input wr;
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input rd;
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input rd;
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input [WID-1:0] din;
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input [WID-1:0] din;
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output [WID-1:0] dout;
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output [WID-1:0] dout;
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output [pCtrBits:0] ctr;
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output [pCtrBits-1:0] ctr;
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reg [pCtrBits:0] ctr;
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reg [pCtrBits-1:0] ctr;
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output full;
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output full;
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output empty;
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output empty;
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assign full = ctr=={pCtrBits{1'b1}}-1;
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assign full = ctr=={pCtrBits{1'b1}}-1;
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assign empty = ctr=={pCtrBits{1'b1}};
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assign empty = ctr=={pCtrBits{1'b1}};
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