| Line 65... |
Line 65... |
reg overrun;
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reg overrun;
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reg [9:0] cnt; // sample bit rate counter / timeout counter
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reg [9:0] cnt; // sample bit rate counter / timeout counter
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reg [10:0] rx_data; // working receive data register
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reg [10:0] rx_data; // working receive data register
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reg [9:0] t2; // data minus stop bit(s)
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reg [9:0] t2; // data minus stop bit(s)
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reg [7:0] t3,t4; // data minus parity bit and start bit
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reg [7:0] t3,t4; // data minus parity bit and start bit
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reg [7:0] t5;
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reg p1;
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reg p1;
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reg gerr; // global error status
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reg gerr; // global error status
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reg perr; // parity error
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reg perr; // parity error
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reg ferr = 1'b0; // framing error
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reg ferr = 1'b0; // framing error
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wire bz; // break detected
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wire bz; // break detected
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reg state; // state machine
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reg state; // state machine
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reg wf; // fifo write
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reg wf; // fifo write
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wire empty;
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wire empty;
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reg didRd;
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reg didRd;
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wire [7:0] dout1;
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reg full1;
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wire fifoFull, fifoEmpty;
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assign ack = cyc & cs;
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assign ack = cyc & cs;
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wire pe_rd;
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wire pe_rd;
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edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & ~wr), .pe(pe_rd), .ne(), .ee());
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edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & ~wr), .pe(pe_rd), .ne(), .ee());
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| Line 90... |
Line 94... |
.clk(clk),
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.clk(clk),
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.rst(rst|clear|fifoClear),
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.rst(rst|clear|fifoClear),
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.wr(wf),
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.wr(wf),
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.rd(rdf),
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.rd(rdf),
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.din({bz,perr,ferr,t4}),
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.din({bz,perr,ferr,t4}),
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.dout({break_o,parityErr,frameErr,dout}),
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.dout({break_o,parityErr,frameErr,dout1}),
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.ctr(qcnt),
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.ctr(qcnt),
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.full(full),
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.full(fifoFull),
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.empty(empty)
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.empty(fifoEmpty)
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);
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);
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assign dout = fifoEnable ? dout1 : t5;
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assign empty = fifoEnable ? fifoEmpty : ~full1;
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assign full = fifoEnable ? fifoFull : full1;
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// compute 1/2 the length of the last bit
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// compute 1/2 the length of the last bit
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// needed for framing error detection
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// needed for framing error detection
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reg [7:0] halfLastBit;
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reg [7:0] halfLastBit;
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always @(stop_bits)
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always @(stop_bits)
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if (stop_bits==3'd3) // 1.5 stop bits ?
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if (stop_bits==3'd3) // 1.5 stop bits ?
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| Line 126... |
Line 134... |
else
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else
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t2 <= {rx_data[8:0],1'b0};
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t2 <= {rx_data[8:0],1'b0};
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// grab the parity bit
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// grab the parity bit
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always @(t2)
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always @(t2)
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p1 <= t2[33];
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p1 <= t2[9];
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// strip off parity and start bit
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// strip off parity and start bit
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always @(parityCtrl or t2)
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always @(parityCtrl or t2)
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if (parityCtrl[0])
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if (parityCtrl[0])
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t3 <= t2[8:1];
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t3 <= t2[8:1];
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| Line 255... |
Line 263... |
end
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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t5 <= 1'b0;
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else begin
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if (wf)
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t5 <= t4;
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end
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always @(posedge clk)
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if (rst)
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full1 <= 1'b0;
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else begin
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if (wf)
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full1 <= 1'b1;
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else if (pe_rd)
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full1 <= 1'b0;
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end
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always @(posedge clk)
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if (rst)
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didRd <= 1'b0;
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didRd <= 1'b0;
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else begin
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else begin
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// set a read flag for later reference
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// set a read flag for later reference
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if (pe_rd)
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if (pe_rd)
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didRd <= 1'b1;
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didRd <= 1'b1;
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