| Line 64... |
Line 64... |
output frameErr; // framing error
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output frameErr; // framing error
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output overrun; // receiver overrun
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output overrun; // receiver overrun
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output parityErr; // parity error
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output parityErr; // parity error
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output break_o; // break detected
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output break_o; // break detected
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output gerr; // global error indicator
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output gerr; // global error indicator
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output [3:0] qcnt; // count of number of words queued
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output [5:0] qcnt; // count of number of words queued
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output [10:0] cnt; // receiver counter
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output [10:0] cnt; // receiver counter
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output bitStream; // received bit stream
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output bitStream; // received bit stream
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|
|
//0 - simple sampling at middle of symbol period
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//0 - simple sampling at middle of symbol period
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//>0 - sampling of 3 middle ticks of sumbol perion and results as majority
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//>0 - sampling of 3 middle ticks of sumbol perion and results as majority
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| Line 93... |
Line 93... |
reg didRd;
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reg didRd;
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wire [11:0] dout1;
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wire [11:0] dout1;
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reg full1;
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reg full1;
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wire fifoFull, fifoEmpty;
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wire fifoFull, fifoEmpty;
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|
|
assign ack = cyc & cs;
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ack_gen #(
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.READ_STAGES(1),
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.WRITE_STAGES(0),
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.REGISTER_OUTPUT(1)
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) uag1
|
|
(
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.rst_i(rst),
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.clk_i(clk),
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.ce_i(1'b1),
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.i(cs & cyc & ~wr),
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.we_i(cs & cyc & wr),
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.o(ack),
|
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.rid_i(0),
|
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.wid_i(0),
|
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.rid_o(),
|
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.wid_o()
|
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);
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|
|
wire pe_rd, pe_wf;
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wire pe_rd, pe_wf;
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edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & ~wr), .pe(pe_rd), .ne(), .ee());
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edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(cs & cyc & ~wr), .pe(pe_rd), .ne(), .ee());
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edge_det ued2 (.rst(rst), .clk(clk), .ce(1'b1), .i(wf), .pe(pe_wf), .ne(), .ee());
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edge_det ued2 (.rst(rst), .clk(clk), .ce(1'b1), .i(wf), .pe(pe_wf), .ne(), .ee());
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|
|
assign bitStream = rx_data[14];
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assign bitStream = rx_data[14];
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assign bz = t3==12'd0;
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assign bz = t3==12'd0;
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wire rdf = fifoEnable ? pe_rd : pe_wf;
|
wire rdf = fifoEnable ? pe_rd : pe_wf;
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|
|
uart6551Fifo #(.WID(15)) uf1
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// Distributed RAM fifo (vendor supplied):
|
|
// First word fall-through
|
|
// 64 entries deep
|
|
// 15 bits wide
|
|
uart6551RxFifo uf1
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst|clear|fifoClear),
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.srst(rst|clear|fifoClear),
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.wr(wf),
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.wr_en(wf),
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.rd(rdf),
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.rd_en(rdf),
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.din({bz,perr,ferr,t3}),
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.din({bz,perr,ferr,t3}),
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.dout({break_o,parityErr,frameErr,dout1}),
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.dout({break_o,parityErr,frameErr,dout1}),
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.ctr(qcnt),
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.data_count(qcnt),
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.full(fifoFull),
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.full(fifoFull),
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.empty(fifoEmpty)
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.empty(fifoEmpty)
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);
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);
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|
|
assign dout = fifoEnable ? dout1 : t5;
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assign dout = fifoEnable ? dout1 : t5;
|
