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https://opencores.org/ocsvn/uart6551/uart6551/trunk
[/] [uart6551/] [trunk/] [trunk/] [rtl/] [uart6551Tx.sv] - Diff between revs 9 and 13
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| Rev 9 |
Rev 13 |
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Line 1... |
// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2004-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2004-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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//
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//
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Line 87... |
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if (awr) fdo2 <= {3'd0,din};
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if (awr) fdo2 <= {3'd0,din};
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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begin
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if (rst)
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empty <= 1;
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else begin
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if (awr) empty <= 0;
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if (awr) empty <= 0;
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else if (rd) empty <= 1;
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else if (rd) empty <= 1;
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end
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end
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assign full = ~empty;
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assign full = ~empty;
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Line 110... |
else begin
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else begin
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if (awr) fempty2 <= 0;
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if (awr) fempty2 <= 0;
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else if (rd) fempty2 <= 1;
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else if (rd) fempty2 <= 1;
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end
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end
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wire [7:0] fdo1; // fifo data output
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wire [7:0] fdo1; // fifo data output
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wire rdf = fifoEnable ? rd : awr;
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wire rdf = fifoEnable ? rd : awr;
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wire fempty;
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wire fempty;
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wire ffull;
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wire ffull;
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uart6551Fifo #(.WID(8)) fifo0
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uart6551Fifo #(.WID(8)) fifo0
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