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Line 22... |
// ============================================================================
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// ============================================================================
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//
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//
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`define IDLE 0
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`define IDLE 0
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`define CNT 1
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`define CNT 1
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//`define UART_NO_TX_FIFO 1'b1
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module uart6551Tx(rst, clk, cyc, cs, wr, din, ack,
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module uart6551Tx(rst, clk, cyc, cs, wr, din, ack,
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fifoEnable, fifoClear, txBreak,
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fifoEnable, fifoClear, txBreak,
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frameSize, wordLength, parityCtrl, baud16x_ce,
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frameSize, wordLength, parityCtrl, baud16x_ce,
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cts, clear, txd, full, empty, qcnt);
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cts, clear, txd, full, empty, qcnt);
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Line 63... |
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assign ack = cyc & cs;
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assign ack = cyc & cs;
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edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & wr), .pe(awr), .ne(), .ee());
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edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & wr), .pe(awr), .ne(), .ee());
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`ifdef UART_NO_TX_FIFO
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`ifdef UART_NO_TX_FIFO
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reg [7:0] fdo;
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reg [7:0] fdo2;
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reg empty;
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reg empty;
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always @(posedge clk)
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always @(posedge clk)
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if (awr) fdo <= {3'd0,din};
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if (awr) fdo2 <= {3'd0,din};
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (awr) empty <= 0;
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if (awr) empty <= 0;
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else if (rd) empty <= 1;
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else if (rd) empty <= 1;
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end
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end
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assign full = ~empty;
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assign full = ~empty;
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wire [7:0] fdo = fdo2;
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`else
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`else
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reg [7:0] fdo2;
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always @(posedge clk)
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if (awr) fdo2 <= {3'd0,din};
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// generate an empty signal for when the fifo is disabled
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// generate an empty signal for when the fifo is disabled
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reg fempty2;
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reg fempty2;
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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fempty2 <= 1;
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fempty2 <= 1;
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if (awr) fempty2 <= 0;
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if (awr) fempty2 <= 0;
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else if (rd) fempty2 <= 1;
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else if (rd) fempty2 <= 1;
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end
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end
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wire [7:0] fdo; // fifo data output
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wire [7:0] fdo1; // fifo data output
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wire rdf = fifoEnable ? rd : awr;
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wire rdf = fifoEnable ? rd : awr;
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wire fempty;
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wire fempty;
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wire ffull;
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wire ffull;
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uart6551Fifo #(.WID(8)) fifo0
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uart6551Fifo #(.WID(8)) fifo0
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(
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(
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.clk(clk),
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.clk(clk),
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.rst(rst|clear|fifoClear),
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.rst(rst|clear|fifoClear),
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.din(din),
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.din(din),
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.wr(awr),
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.wr(awr),
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.rd(rdf),
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.rd(rdf),
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.dout(fdo),
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.dout(fdo1),
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.full(ffull),
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.full(ffull),
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.empty(fempty),
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.empty(fempty),
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.ctr(qcnt)
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.ctr(qcnt)
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);
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);
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assign empty = fifoEnable ? fempty : fempty2;
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assign empty = fifoEnable ? fempty : fempty2;
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assign full = fifoEnable ? ffull : ~fempty2;
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assign full = fifoEnable ? ffull : ~fempty2;
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wire [7:0] fdo = fifoEnable ? fdo1 : fdo2;
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`endif
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`endif
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// mask transmit data for word length
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// mask transmit data for word length
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// this mask is needed for proper parity generation
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// this mask is needed for proper parity generation
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integer n;
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integer n;
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reg [7:0] mask;
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reg [7:0] mask;
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always @*
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always @*
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