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[/] [uart6551/] [trunk/] [trunk/] [rtl/] [uart6551Tx_x12.sv] - Diff between revs 5 and 6

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Rev 5 Rev 6
Line 33... Line 33...
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// ============================================================================
// ============================================================================
//
//
`define IDLE    0
`define IDLE    0
`define CNT             1
`define READ1   1
 
`define READ2   2
 
`define CNT             3
 
 
//`define UART_NO_TX_FIFO       1'b1
//`define UART_NO_TX_FIFO       1'b1
 
 
module uart6551Tx_x12 (rst, clk, cyc, cs, wr, din, ack,
module uart6551Tx_x12 (rst, clk, cyc, cs, wr, din, ack,
        fifoEnable, fifoClear, txBreak,
        fifoEnable, fifoClear, txBreak,
Line 62... Line 64...
input cts;                      // clear to send
input cts;                      // clear to send
input clear;            // clear transmitter
input clear;            // clear transmitter
output reg txd;         // external serial output
output reg txd;         // external serial output
output full;            // fifo is full
output full;            // fifo is full
output empty;           // fifo is empty
output empty;           // fifo is empty
output [3:0] qcnt;      // number of characters queued
output [5:0] qcnt;      // number of characters queued
 
 
reg [11:0] t1;
reg [11:0] t1;
reg [15:0] t2;
reg [15:0] t2;
reg [15:0] tx_data;     // transmit data working reg (raw)
reg [15:0] tx_data;     // transmit data working reg (raw)
reg state;                      // state machine state
reg [1:0] state;                // state machine state
reg [8:0] cnt;          // baud clock counter
reg [8:0] cnt;          // baud clock counter
reg rd;
reg rd;
reg p1, p2;                     // parity bit
reg p1, p2;                     // parity bit
 
 
assign ack = cyc & cs;
assign ack = cyc & cs;
Line 93... Line 95...
assign full = ~empty;
assign full = ~empty;
wire [11:0] fdo = fdo2;
wire [11:0] fdo = fdo2;
`else
`else
reg [11:0] fdo2;
reg [11:0] fdo2;
always_ff @(posedge clk)
always_ff @(posedge clk)
        if (awr) fdo2 <= {3'd0,din};
        if (awr) fdo2 <= din;
// generate an empty signal for when the fifo is disabled
// generate an empty signal for when the fifo is disabled
reg fempty2;
reg fempty2;
always_ff @(posedge clk)
always_ff @(posedge clk)
        if (rst)
        if (rst)
                fempty2 <= 1;
                fempty2 <= 1;
Line 109... Line 111...
 
 
wire [11:0] fdo1;               // fifo data output
wire [11:0] fdo1;               // fifo data output
wire rdf = fifoEnable ? rd : awr;
wire rdf = fifoEnable ? rd : awr;
wire fempty;
wire fempty;
wire ffull;
wire ffull;
uart6551Fifo #(.WID(12)) fifo0
// Distributed RAM fifo (vendor supplied):
(
//      Standard fifo
  .clk(clk),
//      64 entries deep
  .rst(rst|clear|fifoClear),
//      12 bits wide
  .din(din),
uart6551TxFifo fifo1 (
  .wr(awr),
  .clk(clk),                // input wire clk
  .rd(rdf),
  .srst(rst|clear|fifoClear),              // input wire srst
  .dout(fdo1),
  .din(din),                // input wire [11 : 0] din
  .full(ffull),
  .wr_en(awr),            // input wire wr_en
  .empty(fempty),
  .rd_en(rdf),            // input wire rd_en
  .ctr(qcnt)
  .dout(fdo1),              // output wire [11 : 0] dout
 
  .full(ffull),              // output wire full
 
  .empty(fempty),            // output wire empty
 
  .data_count(qcnt)  // output wire [4 : 0] data_count
);
);
assign empty = fifoEnable ? fempty : fempty2;
assign empty = fifoEnable ? fempty : fempty2;
assign full = fifoEnable ? ffull : ~fempty2;
assign full = fifoEnable ? ffull : ~fempty2;
wire [11:0] fdo = fifoEnable ? fdo1 : fdo2;
wire [11:0] fdo = fifoEnable ? fdo1 : fdo2;
`endif
`endif
Line 186... Line 191...
                state <= `IDLE;
                state <= `IDLE;
        if (baud16x_ce) begin
        if (baud16x_ce) begin
                case(state)
                case(state)
                `IDLE:
                `IDLE:
                        if ((!empty && cts)||txBreak)
                        if ((!empty && cts)||txBreak)
 
                                state <= `READ1;
 
                `READ1:
 
                        state <= `READ2;
 
                `READ2:
                                state <= `CNT;
                                state <= `CNT;
                `CNT:
                `CNT:
                        if (cnt==frameSize)
                        if (cnt==frameSize)
                                state <= `IDLE;
                                state <= `IDLE;
                endcase
                endcase
Line 232... Line 241...
if (rst)
if (rst)
        tx_data <= 16'hFFFF;
        tx_data <= 16'hFFFF;
else begin
else begin
        if (baud16x_ce) begin
        if (baud16x_ce) begin
                case(state)
                case(state)
                `IDLE:
                `READ2:
                        if ((!empty && cts)||txBreak)
 
                                tx_data <= t2;
                                tx_data <= t2;
                `CNT:
                `CNT:
                        // Shift the data out. LSB first.
                        // Shift the data out. LSB first.
                        if (cnt[3:0]==4'hF)
                        if (cnt[3:0]==4'hF)
                                tx_data <= {1'b1,tx_data[15:1]};
                                tx_data <= {1'b1,tx_data[15:1]};

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