| Line 33... |
Line 33... |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`define IDLE 0
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`define IDLE 0
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`define CNT 1
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`define READ1 1
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`define READ2 2
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`define CNT 3
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//`define UART_NO_TX_FIFO 1'b1
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//`define UART_NO_TX_FIFO 1'b1
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module uart6551Tx_x12 (rst, clk, cyc, cs, wr, din, ack,
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module uart6551Tx_x12 (rst, clk, cyc, cs, wr, din, ack,
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fifoEnable, fifoClear, txBreak,
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fifoEnable, fifoClear, txBreak,
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| Line 62... |
Line 64... |
input cts; // clear to send
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input cts; // clear to send
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input clear; // clear transmitter
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input clear; // clear transmitter
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output reg txd; // external serial output
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output reg txd; // external serial output
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output full; // fifo is full
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output full; // fifo is full
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output empty; // fifo is empty
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output empty; // fifo is empty
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output [3:0] qcnt; // number of characters queued
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output [5:0] qcnt; // number of characters queued
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reg [11:0] t1;
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reg [11:0] t1;
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reg [15:0] t2;
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reg [15:0] t2;
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reg [15:0] tx_data; // transmit data working reg (raw)
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reg [15:0] tx_data; // transmit data working reg (raw)
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reg state; // state machine state
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reg [1:0] state; // state machine state
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reg [8:0] cnt; // baud clock counter
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reg [8:0] cnt; // baud clock counter
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reg rd;
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reg rd;
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reg p1, p2; // parity bit
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reg p1, p2; // parity bit
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assign ack = cyc & cs;
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assign ack = cyc & cs;
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Line 95... |
assign full = ~empty;
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assign full = ~empty;
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wire [11:0] fdo = fdo2;
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wire [11:0] fdo = fdo2;
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`else
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`else
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reg [11:0] fdo2;
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reg [11:0] fdo2;
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if (awr) fdo2 <= {3'd0,din};
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if (awr) fdo2 <= din;
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// generate an empty signal for when the fifo is disabled
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// generate an empty signal for when the fifo is disabled
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reg fempty2;
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reg fempty2;
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if (rst)
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if (rst)
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fempty2 <= 1;
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fempty2 <= 1;
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Line 111... |
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wire [11:0] fdo1; // fifo data output
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wire [11:0] fdo1; // fifo data output
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wire rdf = fifoEnable ? rd : awr;
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wire rdf = fifoEnable ? rd : awr;
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wire fempty;
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wire fempty;
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wire ffull;
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wire ffull;
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uart6551Fifo #(.WID(12)) fifo0
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// Distributed RAM fifo (vendor supplied):
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(
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// Standard fifo
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.clk(clk),
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// 64 entries deep
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.rst(rst|clear|fifoClear),
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// 12 bits wide
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.din(din),
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uart6551TxFifo fifo1 (
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.wr(awr),
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.clk(clk), // input wire clk
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.rd(rdf),
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.srst(rst|clear|fifoClear), // input wire srst
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.dout(fdo1),
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.din(din), // input wire [11 : 0] din
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.full(ffull),
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.wr_en(awr), // input wire wr_en
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.empty(fempty),
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.rd_en(rdf), // input wire rd_en
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.ctr(qcnt)
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.dout(fdo1), // output wire [11 : 0] dout
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.full(ffull), // output wire full
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.empty(fempty), // output wire empty
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.data_count(qcnt) // output wire [4 : 0] data_count
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);
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);
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assign empty = fifoEnable ? fempty : fempty2;
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assign empty = fifoEnable ? fempty : fempty2;
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assign full = fifoEnable ? ffull : ~fempty2;
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assign full = fifoEnable ? ffull : ~fempty2;
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wire [11:0] fdo = fifoEnable ? fdo1 : fdo2;
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wire [11:0] fdo = fifoEnable ? fdo1 : fdo2;
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`endif
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`endif
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Line 191... |
state <= `IDLE;
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state <= `IDLE;
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if (baud16x_ce) begin
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if (baud16x_ce) begin
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case(state)
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case(state)
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`IDLE:
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`IDLE:
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if ((!empty && cts)||txBreak)
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if ((!empty && cts)||txBreak)
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state <= `READ1;
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`READ1:
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state <= `READ2;
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`READ2:
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state <= `CNT;
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state <= `CNT;
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`CNT:
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`CNT:
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if (cnt==frameSize)
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if (cnt==frameSize)
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state <= `IDLE;
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state <= `IDLE;
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endcase
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endcase
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Line 241... |
if (rst)
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if (rst)
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tx_data <= 16'hFFFF;
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tx_data <= 16'hFFFF;
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else begin
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else begin
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if (baud16x_ce) begin
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if (baud16x_ce) begin
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case(state)
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case(state)
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`IDLE:
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`READ2:
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if ((!empty && cts)||txBreak)
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tx_data <= t2;
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tx_data <= t2;
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`CNT:
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`CNT:
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// Shift the data out. LSB first.
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// Shift the data out. LSB first.
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if (cnt[3:0]==4'hF)
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if (cnt[3:0]==4'hF)
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tx_data <= {1'b1,tx_data[15:1]};
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tx_data <= {1'b1,tx_data[15:1]};
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