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[/] [uart6551/] [trunk/] [trunk/] [rtl/] [uart6551_x12.sv] - Diff between revs 5 and 6

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Rev 5 Rev 6
Line 55... Line 55...
        cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,
        cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,
        rxd_i, txd_o, data_present,
        rxd_i, txd_o, data_present,
        rxDRQ_o, txDRQ_o,
        rxDRQ_o, txDRQ_o,
        xclk_i, RxC_i
        xclk_i, RxC_i
);
);
 
parameter CLK_FREQ = 100;
parameter pCounterBits = 24;
parameter pCounterBits = 24;
parameter pFifoSize = 1024;
parameter pFifoSize = 1024;
parameter pClkDiv = 24'd1302;   // 9.6k baud, 200.000MHz clock
parameter pClkDiv = 24'd1302;   // 9.6k baud, 200.000MHz clock
parameter HIGH = 1'b1;
parameter HIGH = 1'b1;
parameter LOW = 1'b0;
parameter LOW = 1'b0;
Line 155... Line 156...
reg deltaRi;
reg deltaRi;
 
 
// fifo
// fifo
reg rxFifoClear;
reg rxFifoClear;
reg txFifoClear;
reg txFifoClear;
reg fifoEnable;
reg rxFifoEnable;
wire [3:0] rxQued;
reg txFifoEnable;
wire [3:0] txQued;
wire [5:0] rxQued;
 
wire [5:0] txQued;
 
 
// test
// test
wire txd1;
wire txd1;
 
 
assign data_present = ~rxEmpty;
assign data_present = ~rxEmpty;
 
 
assign rxITrig = rxQued >= rxThres;
assign rxITrig = rxQued[5:2] >= rxThres;
assign txITrig = txQued <= txThres;
assign txITrig = txQued[5:2] <= txThres;
wire rxDRQ1 = (fifoEnable ? rxITrig : ~rxEmpty);
wire rxDRQ1 = (rxFifoEnable ? rxITrig : ~rxEmpty);
wire txDRQ1 = (fifoEnable ? txITrig : txEmpty);
wire txDRQ1 = (txFifoEnable ? txITrig : txEmpty);
assign rxDRQ_o = dmaEnable & rxDRQ1;
assign rxDRQ_o = dmaEnable & rxDRQ1;
assign txDRQ_o = dmaEnable & txDRQ1;
assign txDRQ_o = dmaEnable & txDRQ1;
wire rxIRQ = rxIe & rxDRQ1;
wire rxIRQ = rxIe & rxDRQ1;
wire txIRQ = txIe & txDRQ1;
wire txIRQ = txIe & txDRQ1;
 
 
Line 230... Line 232...
        .cyc(cyc_i),
        .cyc(cyc_i),
        .cs(rdrx),
        .cs(rdrx),
        .wr(we),
        .wr(we),
        .dout(rx_do),
        .dout(rx_do),
        .ack(),
        .ack(),
        .fifoEnable(fifoEnable),
        .fifoEnable(rxFifoEnable),
        .fifoClear(rxFifoClear),
        .fifoClear(rxFifoClear),
        .clearGErr(1'b0),
        .clearGErr(1'b0),
        .wordLength(wordLength),
        .wordLength(wordLength),
        .parityCtrl(parityCtrl),
        .parityCtrl(parityCtrl),
        .frameSize(frameSize),
        .frameSize(frameSize),
Line 260... Line 262...
        .cyc(cyc_i),
        .cyc(cyc_i),
        .cs(txrx),
        .cs(txrx),
        .wr(we),
        .wr(we),
        .din(dati),
        .din(dati),
        .ack(),
        .ack(),
        .fifoEnable(fifoEnable),
        .fifoEnable(txFifoEnable),
        .fifoClear(txFifoClear),
        .fifoClear(txFifoClear),
        .txBreak(txBreak),
        .txBreak(txBreak),
        .frameSize(frameSize),  // 16 x 10 bits
        .frameSize(frameSize),  // 16 x 10 bits
        .wordLength(wordLength),// 8 bits
        .wordLength(wordLength),// 8 bits
        .parityCtrl(parityCtrl),// no parity
        .parityCtrl(parityCtrl),// no parity
Line 287... Line 289...
// mux the reg outputs
// mux the reg outputs
always_ff @(posedge clk_i)
always_ff @(posedge clk_i)
if (cs) begin
if (cs) begin
        case(adr_h)
        case(adr_h)
        `UART_TRB:      dat_o <= {4'h0,rx_do};  // receiver holding register
        `UART_TRB:      dat_o <= {4'h0,rx_do};  // receiver holding register
        `UART_STAT:     dat_o <= {irq_o,3'h0,irq_o,dsrx[1],dcdx[1],fifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr};
        `UART_STAT:     dat_o <= {irq_o,3'h0,irq_o,dsrx[1],dcdx[1],txFifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr};
        `UART_CMD:      dat_o <= cmd0;
        `UART_CMD:      dat_o <= cmd0;
        `UART_CTRL:     dat_o <= ctrl0;
        `UART_CTRL:     dat_o <= ctrl0;
        `UART_IRQS:     dat_o <= irqStatusReg;
        `UART_IRQS:     dat_o <= irqStatusReg;
        `UART_MS:               dat_o <= modemStatusReg;
        `UART_MS:               dat_o <= modemStatusReg;
        `UART_LS:               dat_o <= lineStatusReg;
        `UART_LS:               dat_o <= lineStatusReg;
Line 335... Line 337...
 
 
        txBreak         <= 1'b0;
        txBreak         <= 1'b0;
        // Fifo control
        // Fifo control
        txFifoClear     <= 1'b1;
        txFifoClear     <= 1'b1;
        rxFifoClear <= 1'b1;
        rxFifoClear <= 1'b1;
        fifoEnable      <= 1'b1;
        rxFifoEnable    <= 1'b1;
 
        txFifoEnable    <= 1'b1;
        // Test
        // Test
        llb                     <= 1'b0;
        llb                     <= 1'b0;
        selCD           <= 1'b0;
        selCD           <= 1'b0;
        accessCD   <= 1'b0;
        accessCD   <= 1'b0;
end
end
Line 416... Line 419...
                // Extended word length, values beyond 11 not supported.
                // Extended word length, values beyond 11 not supported.
                ctrl1 <= dati;
                ctrl1 <= dati;
        `UART_CTRL2:
        `UART_CTRL2:
        begin
        begin
                ctrl2 <= dati;
                ctrl2 <= dati;
        fifoEnable <= dati[0];
        rxFifoEnable <= dati[0];
        rxFifoClear <= dati[1];
        txFifoEnable <= dati[1];
        txFifoClear <= dati[2];
        rxFifoClear <= dati[2];
 
        txFifoClear <= dati[3];
        case (dati[5:4])
        case (dati[5:4])
        2'd0:   txThres <= 4'd1;                // one-byte
        2'd0:   txThres <= 4'd1;                // one-byte
        2'd1:   txThres <= pFifoSize / 4;       // one-quarter full
        2'd1:   txThres <= pFifoSize / 4;       // one-quarter full
        2'd2:   txThres <= pFifoSize / 2;       // one-half full
        2'd2:   txThres <= pFifoSize / 2;       // one-half full
        2'd3:   txThres <= pFifoSize * 3 / 4;   // three-quarters full
        2'd3:   txThres <= pFifoSize * 3 / 4;   // three-quarters full
Line 455... Line 459...
 
 
always_ff @(posedge clk_i)
always_ff @(posedge clk_i)
        xClkSrc <= baudRateSel==5'd0;
        xClkSrc <= baudRateSel==5'd0;
 
 
wire [pCounterBits-1:0] bclkdiv;
wire [pCounterBits-1:0] bclkdiv;
uart6551BaudLUT #(pCounterBits) ublt1 (.a(baudRateSel), .o(bclkdiv));
uart6551BaudLUT #(
 
        .CLK_FREQ(CLK_FREQ),
 
        .pCounterBits(pCounterBits)
 
) ublt1 (.a(baudRateSel), .o(bclkdiv));
 
 
reg [pCounterBits-1:0] clkdiv2;
reg [pCounterBits-1:0] clkdiv2;
always_ff @(posedge clk_i)
always_ff @(posedge clk_i)
        clkdiv2 <= selCD ? clkdiv : bclkdiv;
        clkdiv2 <= selCD ? clkdiv : bclkdiv;
 
 

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