| Line 55... |
Line 55... |
cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,
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cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,
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rxd_i, txd_o, data_present,
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rxd_i, txd_o, data_present,
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rxDRQ_o, txDRQ_o,
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rxDRQ_o, txDRQ_o,
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xclk_i, RxC_i
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xclk_i, RxC_i
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);
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);
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parameter CLK_FREQ = 100;
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parameter pCounterBits = 24;
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parameter pCounterBits = 24;
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parameter pFifoSize = 1024;
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parameter pFifoSize = 1024;
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parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock
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parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock
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parameter HIGH = 1'b1;
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parameter HIGH = 1'b1;
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parameter LOW = 1'b0;
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parameter LOW = 1'b0;
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| Line 155... |
Line 156... |
reg deltaRi;
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reg deltaRi;
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// fifo
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// fifo
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reg rxFifoClear;
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reg rxFifoClear;
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reg txFifoClear;
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reg txFifoClear;
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reg fifoEnable;
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reg rxFifoEnable;
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wire [3:0] rxQued;
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reg txFifoEnable;
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wire [3:0] txQued;
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wire [5:0] rxQued;
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wire [5:0] txQued;
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// test
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// test
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wire txd1;
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wire txd1;
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assign data_present = ~rxEmpty;
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assign data_present = ~rxEmpty;
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assign rxITrig = rxQued >= rxThres;
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assign rxITrig = rxQued[5:2] >= rxThres;
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assign txITrig = txQued <= txThres;
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assign txITrig = txQued[5:2] <= txThres;
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wire rxDRQ1 = (fifoEnable ? rxITrig : ~rxEmpty);
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wire rxDRQ1 = (rxFifoEnable ? rxITrig : ~rxEmpty);
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wire txDRQ1 = (fifoEnable ? txITrig : txEmpty);
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wire txDRQ1 = (txFifoEnable ? txITrig : txEmpty);
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assign rxDRQ_o = dmaEnable & rxDRQ1;
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assign rxDRQ_o = dmaEnable & rxDRQ1;
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assign txDRQ_o = dmaEnable & txDRQ1;
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assign txDRQ_o = dmaEnable & txDRQ1;
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wire rxIRQ = rxIe & rxDRQ1;
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wire rxIRQ = rxIe & rxDRQ1;
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wire txIRQ = txIe & txDRQ1;
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wire txIRQ = txIe & txDRQ1;
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| Line 230... |
Line 232... |
.cyc(cyc_i),
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.cyc(cyc_i),
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.cs(rdrx),
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.cs(rdrx),
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.wr(we),
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.wr(we),
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.dout(rx_do),
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.dout(rx_do),
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.ack(),
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.ack(),
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.fifoEnable(fifoEnable),
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.fifoEnable(rxFifoEnable),
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.fifoClear(rxFifoClear),
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.fifoClear(rxFifoClear),
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.clearGErr(1'b0),
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.clearGErr(1'b0),
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.wordLength(wordLength),
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.wordLength(wordLength),
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.parityCtrl(parityCtrl),
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.parityCtrl(parityCtrl),
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.frameSize(frameSize),
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.frameSize(frameSize),
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| Line 260... |
Line 262... |
.cyc(cyc_i),
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.cyc(cyc_i),
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.cs(txrx),
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.cs(txrx),
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.wr(we),
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.wr(we),
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.din(dati),
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.din(dati),
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.ack(),
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.ack(),
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.fifoEnable(fifoEnable),
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.fifoEnable(txFifoEnable),
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.fifoClear(txFifoClear),
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.fifoClear(txFifoClear),
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.txBreak(txBreak),
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.txBreak(txBreak),
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.frameSize(frameSize), // 16 x 10 bits
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.frameSize(frameSize), // 16 x 10 bits
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.wordLength(wordLength),// 8 bits
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.wordLength(wordLength),// 8 bits
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.parityCtrl(parityCtrl),// no parity
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.parityCtrl(parityCtrl),// no parity
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| Line 287... |
Line 289... |
// mux the reg outputs
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// mux the reg outputs
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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if (cs) begin
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if (cs) begin
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case(adr_h)
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case(adr_h)
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`UART_TRB: dat_o <= {4'h0,rx_do}; // receiver holding register
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`UART_TRB: dat_o <= {4'h0,rx_do}; // receiver holding register
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`UART_STAT: dat_o <= {irq_o,3'h0,irq_o,dsrx[1],dcdx[1],fifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr};
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`UART_STAT: dat_o <= {irq_o,3'h0,irq_o,dsrx[1],dcdx[1],txFifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr};
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`UART_CMD: dat_o <= cmd0;
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`UART_CMD: dat_o <= cmd0;
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`UART_CTRL: dat_o <= ctrl0;
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`UART_CTRL: dat_o <= ctrl0;
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`UART_IRQS: dat_o <= irqStatusReg;
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`UART_IRQS: dat_o <= irqStatusReg;
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`UART_MS: dat_o <= modemStatusReg;
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`UART_MS: dat_o <= modemStatusReg;
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`UART_LS: dat_o <= lineStatusReg;
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`UART_LS: dat_o <= lineStatusReg;
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| Line 335... |
Line 337... |
|
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txBreak <= 1'b0;
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txBreak <= 1'b0;
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// Fifo control
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// Fifo control
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txFifoClear <= 1'b1;
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txFifoClear <= 1'b1;
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rxFifoClear <= 1'b1;
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rxFifoClear <= 1'b1;
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fifoEnable <= 1'b1;
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rxFifoEnable <= 1'b1;
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txFifoEnable <= 1'b1;
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// Test
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// Test
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llb <= 1'b0;
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llb <= 1'b0;
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selCD <= 1'b0;
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selCD <= 1'b0;
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accessCD <= 1'b0;
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accessCD <= 1'b0;
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end
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end
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| Line 416... |
Line 419... |
// Extended word length, values beyond 11 not supported.
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// Extended word length, values beyond 11 not supported.
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ctrl1 <= dati;
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ctrl1 <= dati;
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`UART_CTRL2:
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`UART_CTRL2:
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begin
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begin
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ctrl2 <= dati;
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ctrl2 <= dati;
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fifoEnable <= dati[0];
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rxFifoEnable <= dati[0];
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rxFifoClear <= dati[1];
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txFifoEnable <= dati[1];
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txFifoClear <= dati[2];
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rxFifoClear <= dati[2];
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txFifoClear <= dati[3];
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case (dati[5:4])
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case (dati[5:4])
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2'd0: txThres <= 4'd1; // one-byte
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2'd0: txThres <= 4'd1; // one-byte
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2'd1: txThres <= pFifoSize / 4; // one-quarter full
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2'd1: txThres <= pFifoSize / 4; // one-quarter full
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2'd2: txThres <= pFifoSize / 2; // one-half full
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2'd2: txThres <= pFifoSize / 2; // one-half full
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2'd3: txThres <= pFifoSize * 3 / 4; // three-quarters full
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2'd3: txThres <= pFifoSize * 3 / 4; // three-quarters full
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| Line 455... |
Line 459... |
|
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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xClkSrc <= baudRateSel==5'd0;
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xClkSrc <= baudRateSel==5'd0;
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|
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wire [pCounterBits-1:0] bclkdiv;
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wire [pCounterBits-1:0] bclkdiv;
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uart6551BaudLUT #(pCounterBits) ublt1 (.a(baudRateSel), .o(bclkdiv));
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uart6551BaudLUT #(
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.CLK_FREQ(CLK_FREQ),
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.pCounterBits(pCounterBits)
|
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) ublt1 (.a(baudRateSel), .o(bclkdiv));
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|
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reg [pCounterBits-1:0] clkdiv2;
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reg [pCounterBits-1:0] clkdiv2;
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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clkdiv2 <= selCD ? clkdiv : bclkdiv;
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clkdiv2 <= selCD ? clkdiv : bclkdiv;
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