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--! @file
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--! @brief Point to point wishbone interconnection (Sample Master with uart_wishbone_slave)
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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entity INTERCON_P2P is
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entity INTERCON_P2P is
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tx: out std_logic;
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tx: out std_logic;
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rx : in std_logic
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rx : in std_logic
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);
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);
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end INTERCON_P2P;
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end INTERCON_P2P;
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--! @brief Declaring the components (SYC0001a, SERIALMASTER, uart_wishbone_slave)
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--! @details Just instantiate and connect the various components
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architecture Behavioral of INTERCON_P2P is
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architecture Behavioral of INTERCON_P2P is
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component SYC0001a
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component SYC0001a
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port(
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port(
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-- WISHBONE Interface
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-- WISHBONE Interface
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CLK_O: out std_logic;
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CLK_O: out std_logic; --! Clock output
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RST_O: out std_logic;
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RST_O: out std_logic; --! Reset output
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-- NON-WISHBONE Signals
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-- NON-WISHBONE Signals
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EXTCLK: in std_logic;
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EXTCLK: in std_logic; --! Clock input
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EXTRST: in std_logic
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EXTRST: in std_logic --! Reset input
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);
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);
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end component SYC0001a;
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end component SYC0001a;
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component SERIALMASTER is
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component SERIALMASTER is
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port(
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port(
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-- WISHBONE Signals
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-- WISHBONE Signals
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ACK_I: in std_logic;
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ACK_I: in std_logic; --! Ack input
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ADR_O: out std_logic_vector( 1 downto 0 );
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ADR_O: out std_logic_vector( 1 downto 0 ); --! Address output
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CLK_I: in std_logic;
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CLK_I: in std_logic; --! Clock input
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CYC_O: out std_logic;
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CYC_O: out std_logic; --! Cycle output
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DAT_I: in std_logic_vector( 31 downto 0 );
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DAT_I: in std_logic_vector( 31 downto 0 ); --! Data input
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DAT_O: out std_logic_vector( 31 downto 0 );
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DAT_O: out std_logic_vector( 31 downto 0 ); --! Data output
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RST_I: in std_logic;
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RST_I: in std_logic; --! Reset input
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SEL_O: out std_logic;
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SEL_O: out std_logic; --! Select output
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STB_O: out std_logic;
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STB_O: out std_logic; --! Strobe output (Works like a chip select)
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WE_O: out std_logic;
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WE_O: out std_logic; --! Write enable
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-- NON-WISHBONE Signals
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-- NON-WISHBONE Signals
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byte_rec : out std_logic_vector(7 downto 0)
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byte_rec : out std_logic_vector(7 downto 0) --! Signal byte received (Used to debug on the out leds)
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);
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);
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end component;
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end component;
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component uart_wishbone_slave is
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component uart_wishbone_slave is
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Port ( RST_I : in STD_LOGIC;
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Port ( RST_I : in STD_LOGIC; --! Reset Input
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CLK_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC; --! Clock Input
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ADR_I0 : in STD_LOGIC_VECTOR (1 downto 0);
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ADR_I0 : in STD_LOGIC_VECTOR (1 downto 0); --! Address input
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DAT_I0 : in STD_LOGIC_VECTOR (31 downto 0);
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DAT_I0 : in STD_LOGIC_VECTOR (31 downto 0); --! Data Input 0
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DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0);
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DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0); --! Data Output 0
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WE_I : in STD_LOGIC;
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WE_I : in STD_LOGIC; --! Write enable input
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STB_I : in STD_LOGIC;
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STB_I : in STD_LOGIC; --! Strobe input (Works like a chip select)
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ACK_O : out STD_LOGIC;
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ACK_O : out STD_LOGIC; --! Ack output
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serial_in : in std_logic;
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data_Avaible : out std_logic;
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-- NON-WISHBONE Signals
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serial_out : out std_logic
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serial_in : in std_logic; --! Uart serial input
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data_Avaible : out std_logic; --! Flag to indicate data avaible
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serial_out : out std_logic --! Uart serial output
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);
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);
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end component;
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end component;
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signal CLK : std_logic;
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signal CLK : std_logic;
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signal RST : std_logic;
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signal RST : std_logic;
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signal ACK : std_logic;
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signal ACK : std_logic;
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signal STB : std_logic;
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signal STB : std_logic;
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signal ADR : std_logic_vector( 1 downto 0 );
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signal ADR : std_logic_vector( 1 downto 0 );
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signal dataI : std_logic_vector (31 downto 0);
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signal dataI : std_logic_vector (31 downto 0);
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signal dataO : std_logic_vector (31 downto 0);
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signal dataO : std_logic_vector (31 downto 0);
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begin
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begin
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--! Instantiate SYC0001a
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uSysCon: component SYC0001a
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uSysCon: component SYC0001a
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port map(
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port map(
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CLK_O => CLK,
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CLK_O => CLK,
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RST_O => RST,
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RST_O => RST,
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EXTCLK => EXTCLK,
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EXTCLK => EXTCLK,
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EXTRST => EXTRST
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EXTRST => EXTRST
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);
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);
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--! Instantiate SERIALMASTER
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uMasterSerial : component SERIALMASTER
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uMasterSerial : component SERIALMASTER
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port map(
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port map(
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ACK_I => ACK,
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ACK_I => ACK,
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ADR_O => ADR,
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ADR_O => ADR,
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CLK_I => CLK,
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CLK_I => CLK,
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STB_O => STB,
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STB_O => STB,
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byte_rec => byte_out,
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byte_rec => byte_out,
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WE_O => WE
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WE_O => WE
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);
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);
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--! Instantiate uart_wishbone_slave
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uUartWishboneSlave: component uart_wishbone_slave
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uUartWishboneSlave: component uart_wishbone_slave
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port map(
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port map(
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RST_I => RST,
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RST_I => RST,
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CLK_I => CLK,
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CLK_I => CLK,
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ADR_I0 => ADR,
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ADR_I0 => ADR,
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