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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [SERIALMASTER.vhd] - Diff between revs 28 and 36

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--! Top wishbone Master to test the uart_wishbone_slave
--! @file
 
--! @brief Top wishbone Master to test the uart_wishbone_slave
library ieee;
library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
 
 
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use work.pkgDefinitions.all;
use work.pkgDefinitions.all;
 
 
entity SERIALMASTER is
entity SERIALMASTER is
        port(
        port(
            -- WISHBONE Signals
            -- WISHBONE Signals
            ACK_I:  in  std_logic;
            ACK_I:  in  std_logic;                                                              --! Ack input
            ADR_O:  out std_logic_vector( 1 downto 0 );
            ADR_O:  out std_logic_vector( 1 downto 0 );  --! Address output
            CLK_I:  in  std_logic;
            CLK_I:  in  std_logic;                                                              --! Clock input
            CYC_O:  out std_logic;
            CYC_O:  out std_logic;                                                              --! Cycle output
            DAT_I:  in  std_logic_vector( 31 downto 0 );
            DAT_I:  in  std_logic_vector( 31 downto 0 ); --! Data input
            DAT_O:  out std_logic_vector( 31 downto 0 );
            DAT_O:  out std_logic_vector( 31 downto 0 ); --! Data output
            RST_I:  in  std_logic;
            RST_I:  in  std_logic;                                                              --! Reset input
            SEL_O:  out std_logic;
            SEL_O:  out std_logic;                                                              --! Select output
            STB_O:  out std_logic;
            STB_O:  out std_logic;                                                              --! Strobe output (Works like a chip select)
            WE_O:   out std_logic;
            WE_O:   out std_logic;                                                              --! Write enable
 
 
                                -- NON-WISHBONE Signals
                                -- NON-WISHBONE Signals
                                byte_rec : out std_logic_vector(7 downto 0)
                                byte_rec : out std_logic_vector(7 downto 0)      --! Signal byte received (Used to debug on the out leds)        
         );
         );
 
 
end SERIALMASTER;
end SERIALMASTER;
 
 
 
--! @brief Test the uart_wishbone_slave
 
--! @details Configure the core then, send the received data back to the PC
architecture Behavioral of SERIALMASTER is
architecture Behavioral of SERIALMASTER is
signal masterSerialStates : testMaster;
signal masterSerialStates : testMaster;
signal byteIncome : std_logic_vector(7 downto 0);
signal byteIncome : std_logic_vector(7 downto 0);
begin
begin
 
 
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                                                        byteIncome <= DAT_I(7 downto 0);
                                                        byteIncome <= DAT_I(7 downto 0);
                                                        cycles2Wait     := 7000000;
                                                        cycles2Wait     := 7000000;
                                                end if;
                                                end if;
 
 
                                        when wait_cycles =>
                                        when wait_cycles =>
                                                -- wait some cycles (90)
                                                -- wait some cycles 
                                                if contWait < cycles2Wait then
                                                if contWait < cycles2Wait then
                                                        contWait := contWait + 1;
                                                        contWait := contWait + 1;
                                                        STB_O <= '0';
                                                        STB_O <= '0';
                                                else
                                                else
                                                        contWait := 0;
                                                        contWait := 0;

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