| Line 32... |
Line 32... |
signal byteIncome : std_logic_vector(7 downto 0);
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signal byteIncome : std_logic_vector(7 downto 0);
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begin
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begin
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process (CLK_I)
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process (CLK_I)
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variable contWait : integer range 0 to 50000000;
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variable contWait : integer range 0 to 50000000;
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variable cycles2Wait : integer range 0 to 50000000;
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variable nextState: testMaster;
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variable nextState: testMaster;
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begin
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begin
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if rising_edge(CLK_I) then
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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if RST_I = '1' then
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masterSerialStates <= idle;
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masterSerialStates <= idle;
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nextState := idle;
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nextState := idle;
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contWait := 0;
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contWait := 0;
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byteIncome <= (others => '0');
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cycles2Wait := 25000000;
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byteIncome <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@';
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else
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else
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case masterSerialStates is
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case masterSerialStates is
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when idle =>
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when idle =>
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masterSerialStates <= config_clock;
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masterSerialStates <= config_clock;
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nextState := idle;
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nextState := idle;
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| Line 80... |
Line 82... |
--DAT_O <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@'
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--DAT_O <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@'
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DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome; --Send the '@'
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DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome; --Send the '@'
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if ACK_I = '1' then
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if ACK_I = '1' then
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-- Byte received wait some cycles to continue
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-- Byte received wait some cycles to continue
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masterSerialStates <= wait_cycles;
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masterSerialStates <= wait_cycles;
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byte_rec <= "00000100";
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cycles2Wait := 7000000;
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end if;
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end if;
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when receive_byte =>
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when receive_byte =>
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nextState := send_byte;
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nextState := send_byte;
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ADR_O <= "11";
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ADR_O <= "11";
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| Line 93... |
Line 95... |
if ACK_I = '1' then
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if ACK_I = '1' then
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-- Byte received wait some cycles to continue
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-- Byte received wait some cycles to continue
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masterSerialStates <= wait_cycles;
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masterSerialStates <= wait_cycles;
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byte_rec <= DAT_I(7 downto 0);
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byte_rec <= DAT_I(7 downto 0);
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byteIncome <= DAT_I(7 downto 0);
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byteIncome <= DAT_I(7 downto 0);
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--byte_rec <= "00001000";
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cycles2Wait := 7000000;
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end if;
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end if;
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when wait_cycles =>
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when wait_cycles =>
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-- wait some cycles (90)
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-- wait some cycles (90)
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if contWait < 25000000 then
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if contWait < cycles2Wait then
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contWait := contWait + 1;
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contWait := contWait + 1;
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STB_O <= '0';
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STB_O <= '0';
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else
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else
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contWait := 0;
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contWait := 0;
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masterSerialStates <= nextState;
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masterSerialStates <= nextState;
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