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--! @file
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-- Module name: SYC0001a.VHD
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--! @brief SYSCON core avaible at: http://www.pldworld.com/_hdl/2/_ip/-silicore.net/wishbone.htm
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--
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-- Description: A simple WISHBONE SYSCON for FPGA. For more infor-
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-- mation, please refer to the WISHBONE Public Domain
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-- Library Technical Reference Manual.
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--
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-- History: Project complete: SEP 20, 2001
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-- WD Peterson
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-- Silicore Corporation
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--
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-- Release: Notice is hereby given that this document is not
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-- copyrighted, and has been placed into the public
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-- domain. It may be freely copied and distributed
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-- by any means.
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--
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-- Disclaimer: In no event shall Silicore Corporation be liable
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-- for incidental, consequential, indirect or special
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-- damages resulting from the use of this file. The
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-- user assumes all responsibility for its use.
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--
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- Load the IEEE 1164 library and make it visible.
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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----------------------------------------------------------------------
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-- Entity declaration.
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----------------------------------------------------------------------
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entity SYC0001a is
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entity SYC0001a is
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port(
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port(
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-- WISHBONE Interface
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-- WISHBONE Interface
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CLK_O: out std_logic; --! Clock output
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CLK_O: out std_logic;
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RST_O: out std_logic; --! Reset output
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RST_O: out std_logic;
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-- NON-WISHBONE Signals
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-- NON-WISHBONE Signals
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EXTCLK: in std_logic; --! Clock input
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EXTCLK: in std_logic;
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EXTRST: in std_logic --! Reset input
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EXTRST: in std_logic
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);
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);
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end SYC0001a;
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end SYC0001a;
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----------------------------------------------------------------------
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-- Architecture definition.
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----------------------------------------------------------------------
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--! @brief Architecture definition. of SYSCON core
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--! @details Architecture definition. of SYSCON core
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architecture SYC0001a1 of SYC0001a IS
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architecture SYC0001a1 of SYC0001a IS
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begin
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begin
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------------------------------------------------------------------
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-- Make selected signals available to the outside world.
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------------------------------------------------------------------
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MAKE_VISIBLE: process( EXTCLK, EXTRST )
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MAKE_VISIBLE: process( EXTCLK, EXTRST )
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begin
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begin
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CLK_O <= EXTCLK;
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CLK_O <= EXTCLK;
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RST_O <= EXTRST;
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RST_O <= EXTRST;
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