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by the Xilinx ISE software. Any direct editing or
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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users do not edit the contents of this file. -->
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Found 32-bit latch for signal <D>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 32-bit latch for signal <N>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 32-bit latch for signal <cycle_wait_oversample>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 32-bit latch for signal <half_cycle>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 32-bit latch for signal <half_cycle0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Signal <byteReceived<7>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Found 8-bit latch for signal <data_byte>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 1-bit latch for signal <Mtridata_byteReceived<0>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 1-bit latch for signal <Mtridata_byteReceived<1>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 1-bit latch for signal <Mtridata_byteReceived<2>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 1-bit latch for signal <Mtridata_byteReceived<3>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 1-bit latch for signal <Mtridata_byteReceived<4>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 1-bit latch for signal <Mtridata_byteReceived<5>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 1-bit latch for signal <Mtridata_byteReceived<6>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 1-bit latch for signal <Mtrien_byteReceived<0>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Found 1-bit latch for signal <Mtrien_byteReceived<1>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Found 1-bit latch for signal <Mtrien_byteReceived<2>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Found 1-bit latch for signal <Mtrien_byteReceived<3>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Found 1-bit latch for signal <Mtrien_byteReceived<4>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Found 1-bit latch for signal <Mtrien_byteReceived<5>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Found 1-bit latch for signal <Mtrien_byteReceived<6>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Signal <sigDivReminder> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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FF/Latch <0> (without init value) has a constant value of 0 in block <30>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <0> (without init value) has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <0> (without init value) has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <0> (without init value) has a constant value of 0 in block <29>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <0> (without init value) has a constant value of 0 in block <30>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <0> (without init value) has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <half_cycle0_29> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <half_cycle_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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The FF/Latch <half_cycle0_7> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <cycle_wait_oversample_8>
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The FF/Latch <half_cycle0_4> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <cycle_wait_oversample_5>
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The FF/Latch <half_cycle0_23> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <cycle_wait_oversample_24>
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The FF/Latch <half_cycle0_28> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <cycle_wait_oversample_29>
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The FF/Latch <half_cycle_1> in Unit <baud_generator> is equivalent to the following FF/Latch, which will be removed : <cycle_wait_oversample_0>
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The FF/Latch <half_cycle0_13> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <cycle_wait_oversample_14>
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The FF/Latch <half_cycle0_18> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <cycle_wait_oversample_19>
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The FF/Latch <half_cycle0_8> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <cycle_wait_oversample_9>
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The FF/Latch <half_cycle0_5> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <cycle_wait_oversample_6>
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The FF/Latch <half_cycle0_24> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <cycle_wait_oversample_25>
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The FF/Latch <half_cycle0_0> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <cycle_wait_oversample_1>
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The FF/Latch <half_cycle0_14> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <cycle_wait_oversample_15>
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The FF/Latch <half_cycle0_19> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <cycle_wait_oversample_20>
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The FF/Latch <half_cycle0_9> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <cycle_wait_oversample_10>
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The FF/Latch <half_cycle0_6> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <cycle_wait_oversample_7>
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The FF/Latch <half_cycle0_25> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <cycle_wait_oversample_26>
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The FF/Latch <half_cycle0_1> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <cycle_wait_oversample_2>
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The FF/Latch <half_cycle0_15> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <cycle_wait_oversample_16>
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The FF/Latch <half_cycle0_20> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <cycle_wait_oversample_21>
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The FF/Latch <half_cycle0_10> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <cycle_wait_oversample_11>
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The FF/Latch <half_cycle0_26> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <cycle_wait_oversample_27>
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The FF/Latch <half_cycle0_2> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <cycle_wait_oversample_3>
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The FF/Latch <half_cycle0_16> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <cycle_wait_oversample_17>
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The FF/Latch <half_cycle0_21> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <cycle_wait_oversample_22>
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The FF/Latch <half_cycle0_11> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <cycle_wait_oversample_12>
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The FF/Latch <half_cycle0_3> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <cycle_wait_oversample_4>
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The FF/Latch <half_cycle0_22> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <cycle_wait_oversample_23>
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The FF/Latch <half_cycle0_27> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <cycle_wait_oversample_28>
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The FF/Latch <half_cycle0_12> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <cycle_wait_oversample_13>
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The FF/Latch <half_cycle0_17> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <cycle_wait_oversample_18>
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Unit serial_receiver: 7 internal tristates are replaced by logic (pull-up yes):
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Node <uUartControl/uDiv/R_31> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_0> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_1> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_2> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_3> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_4> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_5> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_6> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_7> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_8> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_9> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_10> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_11> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_12> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_13> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_14> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_15> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_16> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_17> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_18> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_19> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_20> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_21> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_22> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_23> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_24> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_25> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_26> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_27> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_28> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_29> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_30> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_31> of sequential type is unconnected in block <uart_wishbone_slave>.
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HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
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