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by the Xilinx ISE software. Any direct editing or
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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users do not edit the contents of this file. -->
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"/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" line 53: Unconnected output port 'reminder' of component 'divisor'.
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"E:/uart_block/hdl/iseProject/uart_control.vhd" line 53: Unconnected output port 'reminder' of component 'divisor'.
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The FF/Latch <cycle_wait_oversample_24> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
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"E:/uart_block/hdl/iseProject/uart_control.vhd" line 83: Mux is complete : default of case is discarded
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The FF/Latch <cycle_wait_oversample_7> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
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Unit uart_control: 8 internal tristates are replaced by logic (pull-up yes):
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The FF/Latch <cycle_wait_oversample_19> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
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The FF/Latch <cycle_wait_oversample_20> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
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The FF/Latch <cycle_wait_oversample_15> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
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The FF/Latch <cycle_wait_oversample_0> in Unit <uBaudGen> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
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The FF/Latch <cycle_wait_oversample_29> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
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The FF/Latch <cycle_wait_oversample_3> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
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The FF/Latch <cycle_wait_oversample_27> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
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The FF/Latch <cycle_wait_oversample_23> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
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The FF/Latch <cycle_wait_oversample_8> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
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The FF/Latch <cycle_wait_oversample_5> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
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The FF/Latch <cycle_wait_oversample_18> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
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The FF/Latch <cycle_wait_oversample_14> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
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The FF/Latch <cycle_wait_oversample_28> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
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The FF/Latch <cycle_wait_oversample_26> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
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The FF/Latch <cycle_wait_oversample_1> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
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The FF/Latch <cycle_wait_oversample_22> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
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The FF/Latch <cycle_wait_oversample_17> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
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The FF/Latch <cycle_wait_oversample_31> in Unit <uBaudGen> is equivalent to the following 5 FFs/Latches, which will be removed : <cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29>
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The FF/Latch <cycle_wait_oversample_13> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
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The FF/Latch <cycle_wait_oversample_9> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
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The FF/Latch <cycle_wait_oversample_6> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
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The FF/Latch <cycle_wait_oversample_11> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
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The FF/Latch <cycle_wait_oversample_25> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
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The FF/Latch <cycle_wait_oversample_21> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
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The FF/Latch <cycle_wait_oversample_16> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
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The FF/Latch <cycle_wait_oversample_2> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
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The FF/Latch <cycle_wait_oversample_12> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
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The FF/Latch <cycle_wait_oversample_10> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
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The FF/Latch <cycle_wait_oversample_4> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
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FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <uBaudGen>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <half_cycle_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_29> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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The FF/Latch <cycle_wait_oversample_24> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
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The FF/Latch <cycle_wait_oversample_7> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
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The FF/Latch <cycle_wait_oversample_19> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
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The FF/Latch <cycle_wait_oversample_20> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
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The FF/Latch <cycle_wait_oversample_15> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
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The FF/Latch <cycle_wait_oversample_0> in Unit <baud_generator> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
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The FF/Latch <cycle_wait_oversample_29> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
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The FF/Latch <cycle_wait_oversample_3> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
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The FF/Latch <cycle_wait_oversample_27> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
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The FF/Latch <cycle_wait_oversample_23> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
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The FF/Latch <cycle_wait_oversample_8> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
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The FF/Latch <cycle_wait_oversample_5> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
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The FF/Latch <cycle_wait_oversample_18> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
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The FF/Latch <cycle_wait_oversample_14> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
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The FF/Latch <cycle_wait_oversample_28> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
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The FF/Latch <cycle_wait_oversample_26> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
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The FF/Latch <cycle_wait_oversample_1> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
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The FF/Latch <cycle_wait_oversample_22> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
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The FF/Latch <cycle_wait_oversample_17> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
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The FF/Latch <cycle_wait_oversample_13> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
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The FF/Latch <cycle_wait_oversample_9> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
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The FF/Latch <cycle_wait_oversample_6> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
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The FF/Latch <cycle_wait_oversample_11> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
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The FF/Latch <cycle_wait_oversample_25> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
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The FF/Latch <cycle_wait_oversample_21> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
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The FF/Latch <cycle_wait_oversample_16> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
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The FF/Latch <cycle_wait_oversample_2> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
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The FF/Latch <cycle_wait_oversample_12> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
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The FF/Latch <cycle_wait_oversample_10> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
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The FF/Latch <cycle_wait_oversample_4> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
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The FF/Latch <current_s_FSM_FFd1> in Unit <serial_receiver> is equivalent to the following FF/Latch, which will be removed : <data_ready>
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Node <uUartControl/uDiv/R_31> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uUartControl/uDiv/reminder_0> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_31> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_1> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_30> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_2> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_29> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_3> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_28> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_4> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_27> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_5> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_26> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_6> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_25> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_7> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_24> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_8> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_23> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_9> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_22> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_10> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_21> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_11> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_20> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_12> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_19> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_13> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_18> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_14> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_17> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_15> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_16> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_16> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_15> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_17> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_14> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_18> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_13> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_19> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_12> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_20> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_11> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_21> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_10> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_22> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_9> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_23> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_8> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_24> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_7> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_25> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_6> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_26> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_5> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_27> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_4> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_28> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_3> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_29> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_2> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_30> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_1> of sequential type is unconnected in block <uart_control>.
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Node <uUartControl/uDiv/reminder_31> of sequential type is unconnected in block <uart_wishbone_slave>.
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Node <uDiv/reminder_0> of sequential type is unconnected in block <uart_control>.
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HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
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Node <uDiv/R_31> of sequential type is unconnected in block <uart_control>.
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