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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [_xmsgs/] [xst.xmsgs] - Diff between revs 22 and 24

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Rev 22 Rev 24
Line 3... Line 3...
     by the Xilinx ISE software.  Any direct editing or
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
     users do not edit the contents of this file. -->
 
 
"/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" line 62: Unconnected output port 'reminder' of component 'divisor'.
"/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" line 62: Unconnected output port 'reminder' of component 'divisor'.
 
 
 
 
Node <uDiv/reminder_31> of sequential type is unconnected in block <uart_control>.
Node <uDiv/reminder_31> of sequential type is unconnected in block <uart_control>.
 
 
 
 

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