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by the Xilinx ISE software. Any direct editing or
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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users do not edit the contents of this file. -->
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"E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'CYC_O' of component 'SERIALMASTER'.
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Unit work/INTERCON_P2P is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd".
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"E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'SEL_O' of component 'SERIALMASTER'.
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Unit work/INTERCON_P2P/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd".
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"E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 95: Unconnected output port 'data_Avaible' of component 'uart_wishbone_slave'.
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Unit work/SERIALMASTER is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/SERIALMASTER.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd".
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"E:/uart_block/hdl/iseProject/SERIALMASTER.vhd" line 46: Width mismatch. <byteIncome> has a width of 8 bits but assigned expression is 32-bit wide.
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Unit work/SERIALMASTER/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/SERIALMASTER.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd".
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"E:/uart_block/hdl/iseProject/uart_control.vhd" line 62: Unconnected output port 'reminder' of component 'divisor'.
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Unit work/SYC0001a is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/SYC0001a.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd".
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Unit work/SYC0001a/SYC0001a1 is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/SYC0001a.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd".
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Unit work/uart_wishbone_slave is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd".
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Unit work/uart_wishbone_slave/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd".
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Unit work/uart_communication_blocks is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd".
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Unit work/uart_communication_blocks/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd".
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Unit work/uart_control is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_control.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd".
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Unit work/uart_control/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_control.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd".
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Unit work/baud_generator is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/baud_generator.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd".
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Unit work/baud_generator/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/baud_generator.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd".
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Unit work/divisor is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/divisor.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd".
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Unit work/divisor/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/divisor.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd".
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Unit work/serial_receiver is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/serial_receiver.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".
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Unit work/serial_receiver/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/serial_receiver.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".
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Unit work/serial_transmitter is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/serial_transmitter.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
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Unit work/serial_transmitter/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/serial_transmitter.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
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Unit work/pkgDefinitions is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd".
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Unit work/pkgDefinitions is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd".
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"/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'CYC_O' of component 'SERIALMASTER'.
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"/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'SEL_O' of component 'SERIALMASTER'.
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"/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 95: Unconnected output port 'data_Avaible' of component 'uart_wishbone_slave'.
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"/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd" line 46: Width mismatch. <byteIncome> has a width of 8 bits but assigned expression is 32-bit wide.
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"/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" line 62: Unconnected output port 'reminder' of component 'divisor'.
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Input <DAT_I<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Input <DAT_I<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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