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by the Xilinx ISE software. Any direct editing or
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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users do not edit the contents of this file. -->
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Unit work/INTERCON_P2P is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd".
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"E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'CYC_O' of component 'SERIALMASTER'.
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Unit work/INTERCON_P2P/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd".
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"E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'SEL_O' of component 'SERIALMASTER'.
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Unit work/SERIALMASTER is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/SERIALMASTER.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd".
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"E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 95: Unconnected output port 'data_Avaible' of component 'uart_wishbone_slave'.
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Unit work/SERIALMASTER/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/SERIALMASTER.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd".
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"E:/uart_block/hdl/iseProject/SERIALMASTER.vhd" line 46: Width mismatch. <byteIncome> has a width of 8 bits but assigned expression is 32-bit wide.
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Unit work/SYC0001a is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/SYC0001a.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd".
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"E:/uart_block/hdl/iseProject/uart_control.vhd" line 62: Unconnected output port 'reminder' of component 'divisor'.
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Unit work/SYC0001a/SYC0001a1 is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/SYC0001a.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd".
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Unit work/uart_wishbone_slave is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd".
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Unit work/uart_wishbone_slave/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd".
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Unit work/uart_communication_blocks is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd".
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Unit work/uart_communication_blocks/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd".
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Unit work/uart_control is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_control.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd".
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Unit work/uart_control/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/uart_control.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd".
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Unit work/baud_generator is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/baud_generator.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd".
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Unit work/baud_generator/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/baud_generator.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd".
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Unit work/divisor is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/divisor.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd".
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Unit work/divisor/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/divisor.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd".
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Unit work/serial_receiver is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/serial_receiver.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".
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Unit work/serial_receiver/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/serial_receiver.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".
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Unit work/serial_transmitter is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/serial_transmitter.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
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Unit work/serial_transmitter/Behavioral is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/serial_transmitter.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
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Unit work/pkgDefinitions is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd".
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Unit work/pkgDefinitions is now defined in a different file. It was defined in "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd".
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"/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'CYC_O' of component 'SERIALMASTER'.
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"/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'SEL_O' of component 'SERIALMASTER'.
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"/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 95: Unconnected output port 'data_Avaible' of component 'uart_wishbone_slave'.
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"/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd" line 46: Width mismatch. <byteIncome> has a width of 8 bits but assigned expression is 32-bit wide.
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"/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" line 62: Unconnected output port 'reminder' of component 'divisor'.
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Input <DAT_I<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Input <DAT_I<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Line 27... |
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Output <SEL_O> is never assigned. Tied to value 0.
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Output <SEL_O> is never assigned. Tied to value 0.
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Output <data_avaible> is never assigned.
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Input <baudClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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The FF/Latch <cycle_wait_oversample_24> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
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Signal <getPoint> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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The FF/Latch <cycle_wait_oversample_7> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
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Output <data_avaible> is never assigned.
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The FF/Latch <cycle_wait_oversample_19> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
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The FF/Latch <cycle_wait_oversample_23> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_22>
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The FF/Latch <cycle_wait_oversample_20> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
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The FF/Latch <cycle_wait_oversample_14> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_13>
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The FF/Latch <cycle_wait_oversample_15> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
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The FF/Latch <cycle_wait_oversample_10> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_9>
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The FF/Latch <cycle_wait_oversample_0> in Unit <uBaudGen> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
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The FF/Latch <cycle_wait_oversample_1> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_0>
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The FF/Latch <cycle_wait_oversample_29> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
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The FF/Latch <cycle_wait_oversample_4> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_3>
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The FF/Latch <cycle_wait_oversample_3> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
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The FF/Latch <cycle_wait_oversample_28> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_27>
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The FF/Latch <cycle_wait_oversample_27> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
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The FF/Latch <cycle_wait_oversample_24> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_23>
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The FF/Latch <cycle_wait_oversample_23> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
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The FF/Latch <cycle_wait_oversample_19> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_18>
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The FF/Latch <cycle_wait_oversample_8> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
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The FF/Latch <cycle_wait_oversample_22> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_21>
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The FF/Latch <cycle_wait_oversample_5> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
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The FF/Latch <cycle_wait_oversample_13> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_12>
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The FF/Latch <cycle_wait_oversample_18> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
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The FF/Latch <cycle_wait_oversample_0> in Unit <uBaudGen> is equivalent to the following FF/Latch, which will be removed : <half_cycle_2>
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The FF/Latch <cycle_wait_oversample_14> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
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The FF/Latch <cycle_wait_oversample_27> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_26>
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The FF/Latch <cycle_wait_oversample_28> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
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The FF/Latch <cycle_wait_oversample_2> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_1>
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The FF/Latch <cycle_wait_oversample_26> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
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The FF/Latch <cycle_wait_oversample_29> in Unit <uBaudGen> is equivalent to the following 7 FFs/Latches, which will be removed : <cycle_wait_oversample_31> <cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29> <half_cycle0_28>
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The FF/Latch <cycle_wait_oversample_1> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
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The FF/Latch <cycle_wait_oversample_18> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_17>
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The FF/Latch <cycle_wait_oversample_22> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
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The FF/Latch <cycle_wait_oversample_8> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_7>
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The FF/Latch <cycle_wait_oversample_17> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
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The FF/Latch <cycle_wait_oversample_5> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_4>
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The FF/Latch <cycle_wait_oversample_31> in Unit <uBaudGen> is equivalent to the following 5 FFs/Latches, which will be removed : <cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29>
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The FF/Latch <cycle_wait_oversample_21> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_20>
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The FF/Latch <cycle_wait_oversample_13> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
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The FF/Latch <cycle_wait_oversample_16> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_15>
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The FF/Latch <cycle_wait_oversample_9> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
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The FF/Latch <cycle_wait_oversample_12> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_11>
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The FF/Latch <cycle_wait_oversample_6> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
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The FF/Latch <cycle_wait_oversample_26> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_25>
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The FF/Latch <cycle_wait_oversample_11> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
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The FF/Latch <cycle_wait_oversample_7> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_6>
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The FF/Latch <cycle_wait_oversample_25> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
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The FF/Latch <cycle_wait_oversample_17> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_16>
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The FF/Latch <cycle_wait_oversample_21> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
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The FF/Latch <cycle_wait_oversample_20> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_19>
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The FF/Latch <cycle_wait_oversample_16> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
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The FF/Latch <cycle_wait_oversample_15> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_14>
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The FF/Latch <cycle_wait_oversample_2> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
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The FF/Latch <cycle_wait_oversample_3> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_2>
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The FF/Latch <cycle_wait_oversample_12> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
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The FF/Latch <cycle_wait_oversample_9> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_8>
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The FF/Latch <cycle_wait_oversample_10> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
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The FF/Latch <cycle_wait_oversample_11> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_10>
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The FF/Latch <cycle_wait_oversample_4> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
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The FF/Latch <cycle_wait_oversample_6> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_5>
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The FF/Latch <cycle_wait_oversample_25> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_24>
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FF/Latch <N_24> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <N_24> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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| Line 270... |
Line 207... |
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FF/Latch <config_baud_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <config_baud_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <uBaudGen>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <cycle_wait_oversample_29> (without init value) has a constant value of 0 in block <uBaudGen>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <DAT_O_8> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <DAT_O_8> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
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| Line 456... |
Line 393... |
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Due to other FF/Latch trimming, FF/Latch <DAT_O_31> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <DAT_O_31> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <cycle_wait_oversample_29> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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| Line 474... |
Line 414... |
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_29> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_29> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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The FF/Latch <cycle_wait_oversample_24> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_28> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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The FF/Latch <cycle_wait_oversample_7> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
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The FF/Latch <cycle_wait_oversample_23> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_22>
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The FF/Latch <cycle_wait_oversample_19> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
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The FF/Latch <cycle_wait_oversample_14> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_13>
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The FF/Latch <cycle_wait_oversample_20> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
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The FF/Latch <cycle_wait_oversample_10> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_9>
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The FF/Latch <cycle_wait_oversample_15> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
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The FF/Latch <cycle_wait_oversample_1> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_0>
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The FF/Latch <cycle_wait_oversample_0> in Unit <baud_generator> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
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The FF/Latch <cycle_wait_oversample_4> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_3>
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The FF/Latch <cycle_wait_oversample_29> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
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The FF/Latch <cycle_wait_oversample_28> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_27>
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The FF/Latch <cycle_wait_oversample_3> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
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The FF/Latch <cycle_wait_oversample_24> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_23>
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The FF/Latch <cycle_wait_oversample_27> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
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The FF/Latch <cycle_wait_oversample_19> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_18>
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The FF/Latch <cycle_wait_oversample_23> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
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The FF/Latch <cycle_wait_oversample_22> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_21>
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The FF/Latch <cycle_wait_oversample_8> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
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The FF/Latch <cycle_wait_oversample_13> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_12>
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The FF/Latch <cycle_wait_oversample_5> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
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The FF/Latch <cycle_wait_oversample_0> in Unit <baud_generator> is equivalent to the following FF/Latch, which will be removed : <half_cycle_2>
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The FF/Latch <cycle_wait_oversample_18> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
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The FF/Latch <cycle_wait_oversample_27> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_26>
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The FF/Latch <cycle_wait_oversample_14> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
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The FF/Latch <cycle_wait_oversample_2> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_1>
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The FF/Latch <cycle_wait_oversample_28> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
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The FF/Latch <cycle_wait_oversample_18> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_17>
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The FF/Latch <cycle_wait_oversample_26> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
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The FF/Latch <cycle_wait_oversample_8> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_7>
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The FF/Latch <cycle_wait_oversample_1> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
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The FF/Latch <cycle_wait_oversample_5> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_4>
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The FF/Latch <cycle_wait_oversample_22> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
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The FF/Latch <cycle_wait_oversample_21> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_20>
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The FF/Latch <cycle_wait_oversample_17> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
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The FF/Latch <cycle_wait_oversample_16> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_15>
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The FF/Latch <cycle_wait_oversample_13> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
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The FF/Latch <cycle_wait_oversample_12> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_11>
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The FF/Latch <cycle_wait_oversample_9> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
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The FF/Latch <cycle_wait_oversample_26> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_25>
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The FF/Latch <cycle_wait_oversample_6> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
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The FF/Latch <cycle_wait_oversample_7> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_6>
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The FF/Latch <cycle_wait_oversample_11> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
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The FF/Latch <cycle_wait_oversample_17> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_16>
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The FF/Latch <cycle_wait_oversample_25> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
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The FF/Latch <cycle_wait_oversample_20> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_19>
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The FF/Latch <cycle_wait_oversample_21> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
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The FF/Latch <cycle_wait_oversample_15> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_14>
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The FF/Latch <cycle_wait_oversample_16> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
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The FF/Latch <cycle_wait_oversample_3> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_2>
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The FF/Latch <cycle_wait_oversample_2> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
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The FF/Latch <cycle_wait_oversample_9> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_8>
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The FF/Latch <cycle_wait_oversample_12> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
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The FF/Latch <cycle_wait_oversample_11> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_10>
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The FF/Latch <cycle_wait_oversample_10> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
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The FF/Latch <cycle_wait_oversample_6> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_5>
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The FF/Latch <cycle_wait_oversample_4> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
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The FF/Latch <cycle_wait_oversample_25> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_24>
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FF/Latch <cycles2Wait_0> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <cycles2Wait_0> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
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The FF/Latch <current_s_FSM_FFd1> in Unit <serial_receiver> is equivalent to the following FF/Latch, which will be removed : <data_ready>
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The FF/Latch <current_s_FSM_FFd1> in Unit <serial_receiver> is equivalent to the following FF/Latch, which will be removed : <data_ready>
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Unit uart_control: 32 internal tristates are replaced by logic (pull-up yes):
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Unit uart_control: 32 internal tristates are replaced by logic (pull-up yes):
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FF/Latch <waitBestPoint_3> has a constant value of 0 in block <serial_receiver>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <waitBestPoint_3> has a constant value of 0 in block <serial_receiver>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <waitBestPoint_3> has a constant value of 0 in block <serial_receiver>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
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FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
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