URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [baud_generator.vhd] - Diff between revs 11 and 12

Rev 11	Rev 12
Line 54...	Line 54...
`variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`	`variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`
`begin`	`begin`
`if rst = '1' then`	`if rst = '1' then`
`wait_clk_cycles := (others => '0');`	`wait_clk_cycles := (others => '0');`

`-- Divide cycle_wait by 8`	`-- Divide cycle_wait by 4`
`cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1);`	`cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1);`
`cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);`	`cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);`
`cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);`

`-- Half of cycle_wait_oversample`	`-- Half of cycle_wait_oversample`
`half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);`	`half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);`
`genTickOverSample <= '0';`	`genTickOverSample <= '0';`
`elsif rising_edge(clk) then`	`elsif rising_edge(clk) then`